<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/arch/arm/boot/dts, branch linux-5.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2019-07-26T07:13:02Z</updated>
<entry>
<title>ARM: dts: gemini: Set DIR-685 SPI CS as active low</title>
<updated>2019-07-26T07:13:02Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2019-07-15T20:21:01Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=4c64814abe29c823d9c91818d13996ae5dc81544'/>
<id>urn:sha1:4c64814abe29c823d9c91818d13996ae5dc81544</id>
<content type='text'>
commit f90b8fda3a9d72a9422ea80ae95843697f94ea4a upstream.

The SPI to the display on the DIR-685 is active low, we were
just saved by the SPI library enforcing active low on everything
before, so set it as active low to avoid ambiguity.

Link: https://lore.kernel.org/r/20190715202101.16060-1-linus.walleij@linaro.org
Cc: stable@vger.kernel.org
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Olof Johansson &lt;olof@lixom.net&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>ARM: dts: imx6ul: fix PWM[1-4] interrupts</title>
<updated>2019-07-21T07:01:57Z</updated>
<author>
<name>Sébastien Szymanski</name>
<email>sebastien.szymanski@armadeus.com</email>
</author>
<published>2019-06-18T15:58:34Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=aa08b940a00313b3c6704f5eec15f21ef69b6e5e'/>
<id>urn:sha1:aa08b940a00313b3c6704f5eec15f21ef69b6e5e</id>
<content type='text'>
[ Upstream commit 3cf10132ac8d536565f2c02f60a3aeb315863a52 ]

According to the i.MX6UL/L RM, table 3.1 "ARM Cortex A7 domain interrupt
summary", the interrupts for the PWM[1-4] go from 83 to 86.

Fixes: b9901fe84f02 ("ARM: dts: imx6ul: add pwm[1-4] nodes")
Signed-off-by: Sébastien Szymanski &lt;sebastien.szymanski@armadeus.com&gt;
Reviewed-by: Fabio Estevam &lt;festevam@gmail.com&gt;
Signed-off-by: Shawn Guo &lt;shawnguo@kernel.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>ARM: dts: gemini Fix up DNS-313 compatible string</title>
<updated>2019-07-21T07:01:55Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2019-06-16T21:40:13Z</published>
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<id>urn:sha1:5ac287b813982a90479a4e3a9fd2a9ff023807d3</id>
<content type='text'>
[ Upstream commit 36558020128b1a48b7bddd5792ee70e3f64b04b0 ]

It's a simple typo in the DNS file, which was pretty serious.
No scripts were working properly. Fix it up.

Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>ARM: dts: meson8b: fix the operating voltage of the Mali GPU</title>
<updated>2019-07-21T07:01:53Z</updated>
<author>
<name>Martin Blumenstingl</name>
<email>martin.blumenstingl@googlemail.com</email>
</author>
<published>2019-05-12T19:39:36Z</published>
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<id>urn:sha1:f71b47b37e29099fbf968a48dbbd1bfd99d42bec</id>
<content type='text'>
[ Upstream commit 26d65140e92a626e39c73c9abf769fd174bf5076 ]

Amlogic's vendor kernel defines an OPP for the GPU on Meson8b boards
with a voltage of 1.15V. It turns out that the vendor kernel relies on
the bootloader to set up the voltage. The bootloader however sets a
fixed voltage of 1.10V.

Amlogic's patched u-boot sources (uboot-2015-01-15-23a3562521) confirm
this:
$ grep -oiE "VDD(EE|AO)_VOLTAGE[ ]+[0-9]+" board/amlogic/configs/m8b_*
  board/amlogic/configs/m8b_m100_v1.h:VDDAO_VOLTAGE            1100
  board/amlogic/configs/m8b_m101_v1.h:VDDAO_VOLTAGE            1100
  board/amlogic/configs/m8b_m102_v1.h:VDDAO_VOLTAGE            1100
  board/amlogic/configs/m8b_m200_v1.h:VDDAO_VOLTAGE            1100
  board/amlogic/configs/m8b_m201_v1.h:VDDEE_VOLTAGE            1100
  board/amlogic/configs/m8b_m201_v1.h:VDDEE_VOLTAGE            1100
  board/amlogic/configs/m8b_m202_v1.h:VDDEE_VOLTAGE            1100

Another hint at this is the VDDEE voltage on the EC-100 and Odroid-C1
boards. The VDDEE regulator supplies the Mali GPU. It's basically a copy
of the VCCK (CPU supply) which means it's limited to 0.86V to 1.14V.

Update the operating voltage of the Mali GPU on Meson8b to 1.10V so it
matches with what the vendor u-boot sets.

Fixes: c3ea80b6138cae ("ARM: dts: meson8b: add the Mali-450 MP2 GPU")
Signed-off-by: Martin Blumenstingl &lt;martin.blumenstingl@googlemail.com&gt;
Signed-off-by: Kevin Hilman &lt;khilman@baylibre.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>ARM: dts: meson8: fix GPU interrupts and drop an undocumented property</title>
<updated>2019-07-21T07:01:53Z</updated>
<author>
<name>Martin Blumenstingl</name>
<email>martin.blumenstingl@googlemail.com</email>
</author>
<published>2019-04-20T09:32:57Z</published>
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<id>urn:sha1:eb1cf49961a4d38e8098daecfc2be6589e955ef2</id>
<content type='text'>
[ Upstream commit 01dfdd7b4693496854ac92d1ebfb18d7b108f777 ]

The interrupts in Amlogic's vendor kernel sources are all contiguous.
There are two typos leading to pp2 and pp4 as well as ppmmu2 and ppmmu4
incorrectly sharing the same interrupt line.
Fix this by using interrupt 170 for pp2 and 171 for ppmmu2.

Also drop the undocumented "switch-delay" which is a left-over from my
experiments with an early lima kernel driver when it was still
out-of-tree and required this property on Amlogic SoCs.

Fixes: 7d3f6b536e72c9 ("ARM: dts: meson8: add the Mali-450 MP6 GPU")
Signed-off-by: Martin Blumenstingl &lt;martin.blumenstingl@googlemail.com&gt;
Signed-off-by: Kevin Hilman &lt;khilman@baylibre.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>ARM: dts: am335x phytec boards: Fix cd-gpios active level</title>
<updated>2019-07-14T06:09:40Z</updated>
<author>
<name>Teresa Remmet</name>
<email>t.remmet@phytec.de</email>
</author>
<published>2019-05-24T13:19:57Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=3379bbd0fce938edcb8a35bfe2cb690b888119a8'/>
<id>urn:sha1:3379bbd0fce938edcb8a35bfe2cb690b888119a8</id>
<content type='text'>
[ Upstream commit 8a0098c05a272c9a68f6885e09755755b612459c ]

Active level of the mmc1 cd gpio needs to be low instead of high.
Fix PCM-953 and phyBOARD-WEGA.

Signed-off-by: Teresa Remmet &lt;t.remmet@phytec.de&gt;
Signed-off-by: Tony Lindgren &lt;tony@atomide.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>ARM: dts: Drop bogus CLKSEL for timer12 on dra7</title>
<updated>2019-07-14T06:09:37Z</updated>
<author>
<name>Tony Lindgren</name>
<email>tony@atomide.com</email>
</author>
<published>2019-05-30T07:25:23Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=af5275fc48d2c8e5cd6a72148068be2e9bafc88f'/>
<id>urn:sha1:af5275fc48d2c8e5cd6a72148068be2e9bafc88f</id>
<content type='text'>
[ Upstream commit 34f61de87017aff3c8306280d196dddb1e168a88 ]

There is no CLKSEL for timer12 on dra7 unlike for timer1. This
causes issues on booting the device that Tomi noticed if
DEBUG_SLAB is enabled and the clkctrl clock does not properly
handle non-existing clock. Let's drop the bogus CLKSEL clock,
the clkctrl clock handling gets fixed separately.

Cc: Peter Ujfalusi &lt;peter.ujfalusi@ti.com&gt;
Cc: Tero Kristo &lt;t-kristo@ti.com&gt;
Cc: Tomi Valkeinen &lt;tomi.valkeinen@ti.com&gt;
Reported-by: Tomi Valkeinen &lt;tomi.valkeinen@ti.com&gt;
Tested-by: Tomi Valkeinen &lt;tomi.valkeinen@ti.com&gt;
Tested-by: Peter Ujfalusi &lt;peter.ujfalusi@ti.com&gt;
Fixes: 4ed0dfe3cf39 ("ARM: dts: dra7: Move l4 child devices to probe them with ti-sysc")
Signed-off-by: Tony Lindgren &lt;tony@atomide.com&gt;
Signed-off-by: Sasha Levin &lt;sashal@kernel.org&gt;
</content>
</entry>
<entry>
<title>ARM: dts: armada-xp-98dx3236: Switch to armada-38x-uart serial node</title>
<updated>2019-07-10T07:52:30Z</updated>
<author>
<name>Joshua Scott</name>
<email>joshua.scott@alliedtelesis.co.nz</email>
</author>
<published>2019-06-25T22:11:08Z</published>
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<id>urn:sha1:09cc58c8671330bb46294611e61a498f9e817f17</id>
<content type='text'>
commit 80031361747aec92163464f2ee08870fec33bcb0 upstream.

Switch to the "marvell,armada-38x-uart" driver variant to empty
the UART buffer before writing to the UART_LCR register.

Signed-off-by: Joshua Scott &lt;joshua.scott@alliedtelesis.co.nz&gt;
Tested-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Acked-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;.
Cc: stable@vger.kernel.org
Fixes: 43e28ba87708 ("ARM: dts: Use armada-370-xp as a base for armada-xp-98dx3236")
Signed-off-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>ARM: dts: am57xx-idk: Remove support for voltage switching for SD card</title>
<updated>2019-06-25T03:34:54Z</updated>
<author>
<name>Faiz Abbas</name>
<email>faiz_abbas@ti.com</email>
</author>
<published>2019-05-02T08:47:48Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=e56759725d6e9b641296bcd8deead47d572a162e'/>
<id>urn:sha1:e56759725d6e9b641296bcd8deead47d572a162e</id>
<content type='text'>
commit 88a748419b84187fd1da05637b8e5928b04a1e06 upstream.

If UHS speed modes are enabled, a compatible SD card switches down to
1.8V during enumeration. If after this a software reboot/crash takes
place and on-chip ROM tries to enumerate the SD card, the difference in
IO voltages (host @ 3.3V and card @ 1.8V) may end up damaging the card.

The fix for this is to have support for power cycling the card in
hardware (with a PORz/soft-reset line causing a power cycle of the
card). Since am571x-, am572x- and am574x-idk don't have this
capability, disable voltage switching for these boards.

The major effect of this is that the maximum supported speed
mode is now high speed(50 MHz) down from SDR104(200 MHz).

Cc: &lt;stable@vger.kernel.org&gt;
Signed-off-by: Faiz Abbas &lt;faiz_abbas@ti.com&gt;
Signed-off-by: Tony Lindgren &lt;tony@atomide.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
<entry>
<title>ARM: dts: dra76x: Update MMC2_HS200_MANUAL1 iodelay values</title>
<updated>2019-06-25T03:34:54Z</updated>
<author>
<name>Faiz Abbas</name>
<email>faiz_abbas@ti.com</email>
</author>
<published>2019-04-30T06:08:56Z</published>
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<id>urn:sha1:5cf95590ecee866791172ff4cb273eb6a8e96b34</id>
<content type='text'>
commit c3c0b70cd3f801bded7a548198ee1c9851a0ca82 upstream.

Update the MMC2_HS200_MANUAL1 iodelay values to match with the latest
dra76x data manual[1]. The new iodelay values will have better marginality
and should prevent issues in corner cases.

Also this particular pinctrl-array is using spaces instead of tabs for
spacing between the values and the comments. Fix this as well.

[1] http://www.ti.com/lit/ds/symlink/dra76p.pdf

Cc: &lt;stable@vger.kernel.org&gt;
Signed-off-by: Faiz Abbas &lt;faiz_abbas@ti.com&gt;
[tony@atomide.com: updated description with a bit more info]
Signed-off-by: Tony Lindgren &lt;tony@atomide.com&gt;
Signed-off-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;

</content>
</entry>
</feed>
