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<title>kernel/Documentation/networking/devlink/ice.rst, branch linux-rolling-stable</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
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<updated>2025-02-05T17:02:44Z</updated>
<entry>
<title>ice: devlink PF MSI-X max and min parameter</title>
<updated>2025-02-05T17:02:44Z</updated>
<author>
<name>Michal Swiatkowski</name>
<email>michal.swiatkowski@linux.intel.com</email>
</author>
<published>2024-12-03T06:58:10Z</published>
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<id>urn:sha1:b2657259fce933ae0ba3e07cd0052fb6a8e90689</id>
<content type='text'>
Use generic devlink PF MSI-X parameter to allow user to change MSI-X
range.

Add notes about this parameters into ice devlink documentation.

Tested-by: Pucha Himasekhar Reddy &lt;himasekharx.reddy.pucha@intel.com&gt;
Signed-off-by: Michal Swiatkowski &lt;michal.swiatkowski@linux.intel.com&gt;
Signed-off-by: Tony Nguyen &lt;anthony.l.nguyen@intel.com&gt;
</content>
</entry>
<entry>
<title>ice: Add support for devlink local_forwarding param</title>
<updated>2024-07-11T17:53:57Z</updated>
<author>
<name>Pawel Kaminski</name>
<email>pawel.kaminski@intel.com</email>
</author>
<published>2024-06-07T10:43:49Z</published>
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<id>urn:sha1:a59618b98543248adae7e77d60f67974ca243319</id>
<content type='text'>
Add support for driver-specific devlink local_forwarding param.
Supported values are "enabled", "disabled" and "prioritized".
Default configuration is set to "enabled".

Add documentation in networking/devlink/ice.rst.

In previous generations of Intel NICs the transmit scheduler was only
limited by PCIe bandwidth when scheduling/assigning hairpin-bandwidth
between VFs. Changes to E810 HW design introduced scheduler limitation,
so that available hairpin-bandwidth is bound to external port speed.
In order to address this limitation and enable NFV services such as
"service chaining" a knob to adjust the scheduler config was created.
Driver can send a configuration message to the FW over admin queue and
internal FW logic will reconfigure HW to prioritize and add more BW to
VF to VF traffic. An end result, for example, 10G port will no longer
limit hairpin-bandwidth to 10G and much higher speeds can be achieved.

Devlink local_forwarding param set to "prioritized" enables higher
hairpin-bandwitdh on related PFs. Configuration is applicable only to
8x10G and 4x25G cards.

Changing local_forwarding configuration will trigger CORER reset in
order to take effect.

Example command to change current value:
devlink dev param set pci/0000:b2:00.3 name local_forwarding \
        value prioritized \
        cmode runtime

Co-developed-by: Michal Wilczynski &lt;michal.wilczynski@intel.com&gt;
Signed-off-by: Michal Wilczynski &lt;michal.wilczynski@intel.com&gt;
Reviewed-by: Przemek Kitszel &lt;przemyslaw.kitszel@intel.com&gt;
Signed-off-by: Pawel Kaminski &lt;pawel.kaminski@intel.com&gt;
Signed-off-by: Wojciech Drewek &lt;wojciech.drewek@intel.com&gt;
Tested-by: Rafal Romanowski &lt;rafal.romanowski@intel.com&gt;
Signed-off-by: Tony Nguyen &lt;anthony.l.nguyen@intel.com&gt;
</content>
</entry>
<entry>
<title>ice: Document tx_scheduling_layers parameter</title>
<updated>2024-04-22T20:05:19Z</updated>
<author>
<name>Michal Wilczynski</name>
<email>michal.wilczynski@intel.com</email>
</author>
<published>2024-04-19T08:08:54Z</published>
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<id>urn:sha1:9afff0de30db149a1bf440db26a3ddd6a4f260d8</id>
<content type='text'>
New driver specific parameter 'tx_scheduling_layers' was introduced.
Describe parameter in the documentation.

Signed-off-by: Michal Wilczynski &lt;michal.wilczynski@intel.com&gt;
Acked-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
Reviewed-by: Jiri Pirko &lt;jiri@nvidia.com&gt;
Reviewed-by: Przemek Kitszel &lt;przemyslaw.kitszel@intel.com&gt;
Co-developed-by: Mateusz Polchlopek &lt;mateusz.polchlopek@intel.com&gt;
Signed-off-by: Mateusz Polchlopek &lt;mateusz.polchlopek@intel.com&gt;
Signed-off-by: Tony Nguyen &lt;anthony.l.nguyen@intel.com&gt;
</content>
</entry>
<entry>
<title>ice: add CGU info to devlink info callback</title>
<updated>2023-12-05T10:40:12Z</updated>
<author>
<name>Arkadiusz Kubalewski</name>
<email>arkadiusz.kubalewski@intel.com</email>
</author>
<published>2023-12-01T18:08:40Z</published>
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<id>urn:sha1:b86455a1cbef6829e8da3f93d37a233be2616569</id>
<content type='text'>
If Clock Generation Unit is present on NIC board user shall know its
details.
Provide the devlink info callback with a new:
- fixed type object (cgu.id) indicating hardware variant of onboard CGU,
- running type object (fw.cgu) consisting of CGU id, config and firmware
versions.
These information shall be known for debugging purposes.

Test (on NIC board with CGU)
$ devlink dev info &lt;bus_name&gt;/&lt;dev_name&gt; | grep cgu
        cgu.id 36
        fw.cgu 8032.16973825.6021

Test (on NIC board without CGU)
$ devlink dev info &lt;bus_name&gt;/&lt;dev_name&gt; | grep cgu -c
0

Reviewed-by: Larysa Zaremba &lt;larysa.zaremba@intel.com&gt;
Signed-off-by: Arkadiusz Kubalewski &lt;arkadiusz.kubalewski@intel.com&gt;
Tested-by: Pucha Himasekhar Reddy &lt;himasekharx.reddy.pucha@intel.com&gt; (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen &lt;anthony.l.nguyen@intel.com&gt;
Signed-off-by: Paolo Abeni &lt;pabeni@redhat.com&gt;
</content>
</entry>
<entry>
<title>ice: document RDMA devlink parameters</title>
<updated>2023-04-18T01:53:13Z</updated>
<author>
<name>Jacob Keller</name>
<email>jacob.e.keller@intel.com</email>
</author>
<published>2023-04-14T16:26:14Z</published>
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<id>urn:sha1:1a2bd3bd72e978304cdc0a7385e8048e8242225d</id>
<content type='text'>
Commit e523af4ee560 ("net/ice: Add support for enable_iwarp and enable_roce
devlink param") added support for the enable_roce and enable_iwarp
parameters in the ice driver. It didn't document these parameters in the
ice devlink documentation file. Add this documentation, including a note
about the mutual exclusion between the two modes.

Signed-off-by: Jacob Keller &lt;jacob.e.keller@intel.com&gt;
Reviewed-by: Leon Romanovsky &lt;leonro@nvidia.com&gt;
Acked-by: Tony Nguyen &lt;anthony.l.nguyen@intel.com&gt;
Link: https://lore.kernel.org/r/20230414162614.571861-1-jacob.e.keller@intel.com
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>Documentation: networking: correct spelling</title>
<updated>2023-01-31T12:00:47Z</updated>
<author>
<name>Randy Dunlap</name>
<email>rdunlap@infradead.org</email>
</author>
<published>2023-01-29T23:10:48Z</published>
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<id>urn:sha1:a266ef69b890f099069cf51bb40572611c435a54</id>
<content type='text'>
Correct spelling problems for Documentation/networking/ as reported
by codespell.

Signed-off-by: Randy Dunlap &lt;rdunlap@infradead.org&gt;
Cc: Jonathan Corbet &lt;corbet@lwn.net&gt;
Cc: linux-doc@vger.kernel.org
Cc: Jiri Pirko &lt;jiri@nvidia.com&gt;
Cc: "David S. Miller" &lt;davem@davemloft.net&gt;
Cc: Eric Dumazet &lt;edumazet@google.com&gt;
Cc: Jakub Kicinski &lt;kuba@kernel.org&gt;
Cc: Paolo Abeni &lt;pabeni@redhat.com&gt;
Cc: netdev@vger.kernel.org
Link: https://lore.kernel.org/r/20230129231053.20863-5-rdunlap@infradead.org
Signed-off-by: Paolo Abeni &lt;pabeni@redhat.com&gt;
</content>
</entry>
<entry>
<title>ice: implement direct read for NVM and Shadow RAM regions</title>
<updated>2022-12-01T04:54:31Z</updated>
<author>
<name>Jacob Keller</name>
<email>jacob.e.keller@intel.com</email>
</author>
<published>2022-11-28T20:36:47Z</published>
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<id>urn:sha1:3af4b40b0f2f194d32e90cc5d25ebb3daa96cd1f</id>
<content type='text'>
Implement the .read handler for the NVM and Shadow RAM regions. This
enables user space to read a small chunk of the flash without needing the
overhead of creating a full snapshot.

Update the documentation for ice to detail which regions have direct read
support.

Signed-off-by: Jacob Keller &lt;jacob.e.keller@intel.com&gt;
Acked-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>ice: document 'shadow-ram' devlink region</title>
<updated>2022-12-01T04:54:30Z</updated>
<author>
<name>Jacob Keller</name>
<email>jacob.e.keller@intel.com</email>
</author>
<published>2022-11-28T20:36:46Z</published>
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<id>urn:sha1:2d0197843f9e23c72e3c34303c3a4832bd81b3c3</id>
<content type='text'>
78ad87da9978 ("ice: devlink: add shadow-ram region to snapshot Shadow RAM")
added support for the 'shadow-ram' devlink region, but did not document it
in the ice devlink documentation. Fix this.

Signed-off-by: Jacob Keller &lt;jacob.e.keller@intel.com&gt;
Acked-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>ice: Add documentation for devlink-rate implementation</title>
<updated>2022-11-18T05:43:27Z</updated>
<author>
<name>Michal Wilczynski</name>
<email>michal.wilczynski@intel.com</email>
</author>
<published>2022-11-15T10:48:24Z</published>
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<id>urn:sha1:16eb4afc5d80c40a62d26cd459e89da74d602246</id>
<content type='text'>
Add documentation to a newly added devlink-rate feature. Provide some
examples on how to use the commands, which netlink attributes are
supported and descriptions of the attributes.

Signed-off-by: Michal Wilczynski &lt;michal.wilczynski@intel.com&gt;
Signed-off-by: Jakub Kicinski &lt;kuba@kernel.org&gt;
</content>
</entry>
<entry>
<title>ice: Implement devlink port split operations</title>
<updated>2022-08-24T15:45:55Z</updated>
<author>
<name>Anatolii Gerasymenko</name>
<email>anatolii.gerasymenko@intel.com</email>
</author>
<published>2022-08-11T13:05:35Z</published>
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<id>urn:sha1:26d1c571e16a4ca8c144f6627245eb8209f326c2</id>
<content type='text'>
Allow to configure port split options using the devlink port split
interface. Support port splitting only for port 0, as the FW has
a predefined set of available port split options for the whole device.

Add ice_devlink_port_options_print() function to print the table with
all available FW port split options. It will be printed after each port
split and unsplit command.

Add documentation for devlink port split interface usage for the ice
driver.

Co-developed-by: Jesse Brandeburg &lt;jesse.brandeburg@intel.com&gt;
Signed-off-by: Jesse Brandeburg &lt;jesse.brandeburg@intel.com&gt;
Signed-off-by: Anatolii Gerasymenko &lt;anatolii.gerasymenko@intel.com&gt;
Tested-by: Gurucharan &lt;gurucharanx.g@intel.com&gt; (A Contingent worker at Intel)
Signed-off-by: Tony Nguyen &lt;anthony.l.nguyen@intel.com&gt;
</content>
</entry>
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