kernel/Documentation/memory-barriers.txt, branch 0x221E-v0.0.1-v6.19

memory-barriers.txt: Sort wait_event* and wait_on_bit* list alphabetically

2025-11-09T03:02:26Z

Commit 88172700423c ("docs/memory-barriers.txt: Add wait_event_cmd() and wait_event_exclusive_cmd()") added two APIs without taking care of the list order. Sort the list for readability. While there, make it clear that this is incomplete by saying "for example". Signed-off-by: Akira Yokosawa Reviewed-by: Håkon Bugge Signed-off-by: Paul E. McKenney

docs/memory-barriers.txt: Add wait_event_cmd() and wait_event_exclusive_cmd()

2025-07-09T17:08:14Z

Add said functions to Documentation/memory-barriers.txt. Signed-off-by: Håkon Bugge -- v1 -> v2: * Changed the prosaic part to kernel-doc style and moved it to include/linux/wait.h in another commit Signed-off-by: Paul E. McKenney

docs/memory-barriers.txt: Remove left-over references to "CACHE COHERENCY"

2024-09-14T06:56:44Z

Commit 8ca924aeb4f2 ("Documentation/barriers: Remove references to [smp_]read_barrier_depends()") removed the entire section of "CACHE COHERENCY", without getting rid of its traces. Remove them. Signed-off-by: Akira Yokosawa Cc: Will Deacon Signed-off-by: Paul E. McKenney Acked-by: Andrea Parri

doc: Clarify historical disclaimers in memory-barriers.txt

2023-12-13T19:46:28Z

This commit makes it clear that the reason that these sections are historical is that smp_read_barrier_depends() is no more. It also removes the point about comparison operations, given that there are other optimizations that can break address dependencies. Suggested-by: Jonas Oberhauser Signed-off-by: Paul E. McKenney Cc: Alan Stern Cc: Andrea Parri Cc: Will Deacon Cc: Peter Zijlstra Cc: Boqun Feng Cc: Nicholas Piggin Cc: David Howells Cc: Jade Alglave Cc: Luc Maranget Cc: Akira Yokosawa Cc: Daniel Lustig Cc: Joel Fernandes Cc: Jonathan Corbet Cc: Cc: Signed-off-by: Neeraj Upadhyay (AMD)

docs: memory-barriers: Add note on compiler transformation and address deps

2023-10-09T16:40:53Z

The compiler has the ability to cause misordering by destroying address-dependency barriers if comparison operations are used. Add a note about this to memory-barriers.txt in the beginning of both the historical address-dependency sections and point to rcu-dereference.rst for more information. Signed-off-by: Joel Fernandes (Google) Cc: Alan Stern Cc: Will Deacon Cc: Peter Zijlstra Cc: Boqun Feng Cc: Nicholas Piggin Cc: David Howells Cc: Jade Alglave Cc: Luc Maranget Cc: Akira Yokosawa Cc: Daniel Lustig Cc: Joel Fernandes Cc: Jonathan Corbet Reviewed-by: Andrea Parri Signed-off-by: Paul E. McKenney

locking/memory-barriers.txt: Improve documentation for writel() example

2023-01-04T04:47:04Z

The cited commit describes that when using writel(), explicit wmb() is not needed. wmb() is an expensive barrier. writel() uses the needed platform specific barrier instead of wmb(). writeX() section of "KERNEL I/O BARRIER EFFECTS" already describes ordering of I/O accessors with MMIO writes. Hence add the comment for pseudo code of writel() and remove confusing text around writel() and wmb(). commit 5846581e3563 ("locking/memory-barriers.txt: Fix broken DMA vs. MMIO ordering example") Co-developed-by: Will Deacon Signed-off-by: Will Deacon Signed-off-by: Parav Pandit Signed-off-by: Paul E. McKenney

docs/memory-barriers.txt: Add a missed closing parenthesis

2022-10-18T22:14:52Z

The description of io_stop_wc(), which was added by commit d5624bb29f49 ("asm-generic: introduce io_stop_wc() and add implementation for ARM64"), has an unclosed parenthesis. This commit closes it. Fixes: d5624bb29f49 ("asm-generic: introduce io_stop_wc() and add implementation for ARM64") Signed-off-by: SeongJae Park Signed-off-by: Paul E. McKenney

docs/memory-barriers.txt: Fixup long lines

2022-08-31T12:15:31Z

Substitution of "data dependency barrier" with "address-dependency barrier" left quite a lot of lines exceeding 80 columns. Reflow those lines as well as a few short ones not related to the substitution. No changes in documentation text. Signed-off-by: Akira Yokosawa Cc: "Paul E. McKenney" Cc: Alan Stern Cc: Will Deacon Cc: Peter Zijlstra Cc: Boqun Feng Cc: Andrea Parri Cc: Nicholas Piggin Cc: David Howells Cc: Daniel Lustig Cc: Joel Fernandes Cc: "Michael S. Tsirkin" Cc: Jonathan Corbet Signed-off-by: Paul E. McKenney

docs/memory-barriers.txt: Fix confusing name of 'data dependency barrier'

2022-08-31T12:15:31Z

The term "data dependency barrier", which has been in memory-barriers.txt ever since it was first authored by David Howells, has become confusing due to the fact that in LKMM's explanations.txt and elsewhere, "data dependency" is used mostly for load-to-store data dependency. To prevent further confusions, do the changes listed below: - substitute "data dependency barrier" with "address-dependency barrier"; - add note on the removal of kernel APIs for explicit address- dependency barriers in kernel release v5.9; - note that address-dependency barriers are not necessary for load-to-store situations; - use READ_ONCE_OLD() for pre-4.15 READ_ONCE() (no implicit address- dependency barrier); - fix count of kernel memory barrier APIs; - and a few more context adjustments. Note: Cleanups of long lines are deferred to a followup patch. Reported-by: "Michael S. Tsirkin" Link: https://lore.kernel.org/r/20211011064233-mutt-send-email-mst@kernel.org/ Signed-off-by: Akira Yokosawa Cc: "Paul E. McKenney" Cc: Alan Stern Cc: Will Deacon Cc: Peter Zijlstra Cc: Boqun Feng Cc: Andrea Parri Cc: Nicholas Piggin Cc: David Howells Cc: Daniel Lustig Cc: Joel Fernandes Cc: Jonathan Corbet Signed-off-by: Paul E. McKenney

asm-generic: Add memory barrier dma_mb()

2022-06-23T17:34:58Z

The memory barrier dma_mb() is introduced by commit a76a37777f2c ("iommu/arm-smmu-v3: Ensure queue is read after updating prod pointer"), which is used to ensure that prior (both reads and writes) accesses to memory by a CPU are ordered w.r.t. a subsequent MMIO write. Reviewed-by: Arnd Bergmann # for asm-generic Signed-off-by: Kefeng Wang Reviewed-by: Marco Elver Link: https://lore.kernel.org/r/20220523113126.171714-2-wangkefeng.wang@huawei.com Signed-off-by: Will Deacon