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<title>kernel/Documentation/devicetree/bindings/sram, branch linux-5.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y</id>
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<updated>2019-03-06T18:15:42Z</updated>
<entry>
<title>Merge tag 'armsoc-newsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc</title>
<updated>2019-03-06T18:15:42Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2019-03-06T18:15:42Z</published>
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<id>urn:sha1:64b1b217f1a20f15dbedf47e49a25a0b5ee3d53b</id>
<content type='text'>
Pull ARM new SoC family support from Arnd Bergmann:
 "Two new SoC families are added this time.

  Sugaya Taichi submitted support for the Milbeaut SoC family from
  Socionext and explains:

    "SC2000 is a SoC of the Milbeaut series. equipped with a DSP
     optimized for computer vision. It also features advanced
     functionalities such as 360-degree, real-time spherical stitching
     with multi cameras, image stabilization for without mechanical
     gimbals, and rolling shutter correction. More detail is below:

       https://www.socionext.com/en/products/assp/milbeaut/SC2000.html"

  Interestingly, this one has a history dating back to older chips made
  by Socionext and previously Matsushita/Panasonic based on their own
  mn10300 CPU architecture that was removed from the kernel last year.

  Manivannan Sadhasivam adds support for another SoC family, this is the
  Bitmain BM1880 chip used in the Sophon Edge TPU developer board.

  The chip is intended for Deep Learning applications, and comes with
  dual-core Arm Cortex-A53 to run Linux as well as a RISC-V
  microcontroller core to control the tensor unit. For the moment, the
  TPU is not accessible in mainline Linux, so we treat it as a generic
  Arm SoC.

  More information is available at

       https://www.sophon.ai/"

* tag 'armsoc-newsoc' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc:
  ARM: multi_v7_defconfig: add ARCH_MILBEAUT and ARCH_MILBEAUT_M10V
  ARM: configs: Add Milbeaut M10V defconfig
  ARM: dts: milbeaut: Add device tree set for the Milbeaut M10V board
  clocksource/drivers/timer-milbeaut: Introduce timer for Milbeaut SoCs
  dt-bindings: timer: Add Milbeaut M10V timer description
  ARM: milbeaut: Add basic support for Milbeaut m10v SoC
  dt-bindings: Add documentation for Milbeaut SoCs
  dt-bindings: arm: Add SMP enable-method for Milbeaut
  dt-bindings: sram: milbeaut: Add binding for Milbeaut smp-sram
  MAINTAINERS: Add entry for Bitmain SoC platform
  arm64: dts: bitmain: Add Sophon Egde board support
  arm64: dts: bitmain: Add BM1880 SoC support
  arm64: Add ARCH_BITMAIN platform
  dt-bindings: arm: Document Bitmain BM1880 SoC
</content>
</entry>
<entry>
<title>dt-bindings: sram: milbeaut: Add binding for Milbeaut smp-sram</title>
<updated>2019-03-01T14:18:26Z</updated>
<author>
<name>Sugaya Taichi</name>
<email>sugaya.taichi@socionext.com</email>
</author>
<published>2019-02-27T04:51:49Z</published>
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<id>urn:sha1:1d0bf7b9d308c01113eaead72a5578ca6fc01146</id>
<content type='text'>
The Milbeaut M10V SoC needs a part of sram for smp, so this adds the
M10V sram compatible and binding.

Signed-off-by: Sugaya Taichi &lt;sugaya.taichi@socionext.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>dt-bindings: sram: sunxi: Add compatible for the H6 SRAM C1</title>
<updated>2019-01-29T09:07:26Z</updated>
<author>
<name>Jernej Skrabec</name>
<email>jernej.skrabec@siol.net</email>
</author>
<published>2019-01-28T20:55:02Z</published>
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<id>urn:sha1:4571a7d814add6bddc91594c0d5862df1504c183</id>
<content type='text'>
This introduces a new compatible for the H6 SRAM C1 section, that is
compatible with the SRAM C1 section as found on the A10.

Signed-off-by: Jernej Skrabec &lt;jernej.skrabec@siol.net&gt;
Signed-off-by: Maxime Ripard &lt;maxime.ripard@bootlin.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: sram: sunxi: Add compatible for the A64 SRAM C1</title>
<updated>2018-12-05T11:03:47Z</updated>
<author>
<name>Paul Kocialkowski</name>
<email>paul.kocialkowski@bootlin.com</email>
</author>
<published>2018-12-05T09:24:38Z</published>
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<id>urn:sha1:d44d37cb27df5501de0693fb03803e244653713c</id>
<content type='text'>
This introduces a new compatible for the A64 SRAM C1 section, that is
compatible with the SRAM C1 section as found on the A10.

Signed-off-by: Paul Kocialkowski &lt;paul.kocialkowski@bootlin.com&gt;
Acked-by: Chen-Yu Tsai &lt;wens@csie.org&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Maxime Ripard &lt;maxime.ripard@bootlin.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: sram: sunxi: Add bindings for the H5 with SRAM C1</title>
<updated>2018-12-05T11:03:43Z</updated>
<author>
<name>Paul Kocialkowski</name>
<email>paul.kocialkowski@bootlin.com</email>
</author>
<published>2018-12-05T09:24:34Z</published>
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<id>urn:sha1:ebc0a24d11b3618e7680e117ee3be421c09ad43a</id>
<content type='text'>
This introduces new bindings for the H5 SoC in the SRAM controller.
Because the SRAM layout is different from other SoCs, no backward
compatibility is assumed with any of them.

However, the C1 SRAM section alone looks similar to previous SoCs,
so it is compatible with the initial A10 binding.

Signed-off-by: Paul Kocialkowski &lt;paul.kocialkowski@bootlin.com&gt;
Acked-by: Chen-Yu Tsai &lt;wens@csie.org&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Maxime Ripard &lt;maxime.ripard@bootlin.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: sram: Add Allwinner suniv F1C100s</title>
<updated>2018-12-05T10:58:19Z</updated>
<author>
<name>Mesih Kilinc</name>
<email>mesihkilinc@gmail.com</email>
</author>
<published>2018-12-02T20:23:48Z</published>
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<id>urn:sha1:46d1ec73c19067dad22523632306e3fffedb5f11</id>
<content type='text'>
The suniv ARMv5 F1C100s chip has similar sram controller to sun4i A10.
Add compatible string for it.

Signed-off-by: Mesih Kilinc &lt;mesihkilinc@gmail.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Maxime Ripard &lt;maxime.ripard@bootlin.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: sunxi-sram: add binding for Allwinner H6 SRAM C</title>
<updated>2018-09-12T14:40:26Z</updated>
<author>
<name>Icenowy Zheng</name>
<email>icenowy@aosc.io</email>
</author>
<published>2018-09-02T07:26:17Z</published>
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<id>urn:sha1:69a8c2452caae22008ee170d3ef66e97e9df391e</id>
<content type='text'>
The Allwinner H6 SoC's DE3 needs the SRAM C section being claimed in the
system controller to work, like A64 DE2.

As H6 and A64 system controller are quite similar, code is reused now,
and the A64 fallback compatible string is added after the H6 compatible
string.

Signed-off-by: Icenowy Zheng &lt;icenowy@aosc.io&gt;
[fixed typo in compatible string]
Signed-off-by: Jernej Skrabec &lt;jernej.skrabec@siol.net&gt;
Reviewed-by: Chen-Yu Tsai &lt;wens@csie.org&gt;
Signed-off-by: Chen-Yu Tsai &lt;wens@csie.org&gt;
</content>
</entry>
<entry>
<title>Merge tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc</title>
<updated>2018-08-23T20:52:46Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2018-08-23T20:52:46Z</published>
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<id>urn:sha1:f3ea496213819c80ce9c49a9b65f9261da713d11</id>
<content type='text'>
Pull ARM SoC driver updates from Olof Johansson:
 "Some of the larger changes this merge window:

   - Removal of drivers for Exynos5440, a Samsung SoC that never saw
     widespread use.

   - Uniphier support for USB3 and SPI reset handling

   - Syste control and SRAM drivers and bindings for Allwinner platforms

   - Qualcomm AOSS (Always-on subsystem) reset controller drivers

   - Raspberry Pi hwmon driver for voltage

   - Mediatek pwrap (pmic) support for MT6797 SoC"

* tag 'armsoc-drivers' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (52 commits)
  drivers/firmware: psci_checker: stash and use topology_core_cpumask for hotplug tests
  soc: fsl: cleanup Kconfig menu
  soc: fsl: dpio: Convert DPIO documentation to .rst
  staging: fsl-mc: Remove remaining files
  staging: fsl-mc: Move DPIO from staging to drivers/soc/fsl
  staging: fsl-dpaa2: eth: move generic FD defines to DPIO
  soc: fsl: qe: gpio: Add qe_gpio_set_multiple
  usb: host: exynos: Remove support for Exynos5440
  clk: samsung: Remove support for Exynos5440
  soc: sunxi: Add the A13, A23 and H3 system control compatibles
  reset: uniphier: add reset control support for SPI
  cpufreq: exynos: Remove support for Exynos5440
  ata: ahci-platform: Remove support for Exynos5440
  soc: imx6qp: Use GENPD_FLAG_ALWAYS_ON for PU errata
  soc: mediatek: pwrap: add mt6351 driver for mt6797 SoCs
  soc: mediatek: pwrap: add pwrap driver for mt6797 SoCs
  soc: mediatek: pwrap: fix cipher init setting error
  dt-bindings: pwrap: mediatek: add pwrap support for MT6797
  reset: uniphier: add USB3 core reset control
  dt-bindings: reset: uniphier: add USB3 core reset support
  ...
</content>
</entry>
<entry>
<title>dt-bindings: sram: sunxi: Populate valid sections compatibles</title>
<updated>2018-07-11T08:55:43Z</updated>
<author>
<name>Paul Kocialkowski</name>
<email>paul.kocialkowski@bootlin.com</email>
</author>
<published>2018-07-10T08:00:57Z</published>
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<id>urn:sha1:0ec201cfe7be7d2fd0667450f6214a7f43aa1309</id>
<content type='text'>
This adds a list of valid SRAM sections compatibles for the A13, A20,
A23 and H3 platforms. Per-platform compatibles are introduced for the
SRAM sections of these platforms, with the A10 compatibles also listed
as valid when applicable.

In particular, compatibles for the C1 SRAM section are introduced. Other
SRAMs (C2 and C3 in particular) are left out. They will be added we needed.

Signed-off-by: Paul Kocialkowski &lt;paul.kocialkowski@bootlin.com&gt;
[Maxime: Added the A10 compatible as fallback, not alternatives]
Signed-off-by: Maxime Ripard &lt;maxime.ripard@bootlin.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: sram: sunxi: Add A13, A20, A23 and H3 dedicated bindings</title>
<updated>2018-07-11T08:55:43Z</updated>
<author>
<name>Paul Kocialkowski</name>
<email>paul.kocialkowski@bootlin.com</email>
</author>
<published>2018-07-10T08:00:56Z</published>
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<id>urn:sha1:7d88cd78270ad33cc691b5b0652faff89db8abb4</id>
<content type='text'>
This introduces dedicated bindings for the system control blocks found
on the A13, A20, A23 and H3 sunxi platforms.

Since the controllers on the A33 are the very same as those on the A23,
no specific compatible is introduced for it.

These bindings are introduced to allow reflecting the differences that
exist between these controllers, that may become significant to driver
implementations.

Signed-off-by: Paul Kocialkowski &lt;paul.kocialkowski@bootlin.com&gt;
[Maxime: Added A10 fallback compatible for the A20]
Signed-off-by: Maxime Ripard &lt;maxime.ripard@bootlin.com&gt;
</content>
</entry>
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