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<title>kernel/Documentation/devicetree/bindings/soc/renesas, branch linux-6.2.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.2.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.2.y'/>
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<updated>2022-11-17T19:18:21Z</updated>
<entry>
<title>dt-bindings: arm: renesas: Document Renesas RZ/V2M System Configuration</title>
<updated>2022-11-17T19:18:21Z</updated>
<author>
<name>Phil Edworthy</name>
<email>phil.edworthy@renesas.com</email>
</author>
<published>2022-11-16T10:21:38Z</published>
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<id>urn:sha1:a884f187760ee0c6033296aa50845e2d1e0e8430</id>
<content type='text'>
Add DT binding documentation for System Configuration (SYS) found on
RZ/V2M SoC's.

SYS block contains the SYS_VERSION register which can be used to retrieve
SoC version information.

Signed-off-by: Phil Edworthy &lt;phil.edworthy@renesas.com&gt;
Signed-off-by: Biju Das &lt;biju.das.jz@bp.renesas.com&gt;
Reviewed-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Link: https://lore.kernel.org/r/20221116102140.852889-2-biju.das.jz@bp.renesas.com
Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
</content>
</entry>
<entry>
<title>dt-bindings: soc: renesas: renesas.yaml: Document Renesas RZ/Five SoC</title>
<updated>2022-10-28T12:43:12Z</updated>
<author>
<name>Lad Prabhakar</name>
<email>prabhakar.mahadev-lad.rj@bp.renesas.com</email>
</author>
<published>2022-09-20T18:48:58Z</published>
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<id>urn:sha1:7dd1d57c052e88f98b9e9145461b13bca019d108</id>
<content type='text'>
Document Renesas RZ/Five (R9A07G043) SoC.

More info about RZ/Five SoC:
https://www.renesas.com/us/en/products/microcontrollers-microprocessors/rz-mpus/rzfive-risc-v-general-purpose-microprocessors-risc-v-cpu-core-andes-ax45mp-single-10-ghz-2ch-gigabit-ethernet

Signed-off-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt;
Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Link: https://lore.kernel.org/r/20220920184904.90495-5-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
</content>
</entry>
<entry>
<title>dt-bindings: soc: renesas: Move renesas.yaml from arm to soc</title>
<updated>2022-10-28T12:43:12Z</updated>
<author>
<name>Lad Prabhakar</name>
<email>prabhakar.mahadev-lad.rj@bp.renesas.com</email>
</author>
<published>2022-09-20T18:48:55Z</published>
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<id>urn:sha1:c27ce08b806d606cd5cd0e8252d1ed2b729b5b55</id>
<content type='text'>
renesas.yaml lists out all the Renesas SoC's and the platforms/EVK's which
is either ARM32/ARM64. It would rather make sense if we move renesas.yaml
to the soc/renesas folder instead. This is in preparation for adding a new
SoC (RZ/Five) from Renesas which is based on RISC-V.

While at it drop the old entry for renesas.yaml from MAINTAINERS file and
there is no need to update the new file path of renesas.yaml as we already
have an entry for Documentation/devicetree/bindings/soc/renesas/ folder.

Signed-off-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt;
Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Link: https://lore.kernel.org/r/20220920184904.90495-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
</content>
</entry>
<entry>
<title>dt-bindings: soc: renesas: renesas,rzg2l-sysc: Document RZ/Five SoC</title>
<updated>2022-08-16T07:22:53Z</updated>
<author>
<name>Lad Prabhakar</name>
<email>prabhakar.mahadev-lad.rj@bp.renesas.com</email>
</author>
<published>2022-07-22T14:15:05Z</published>
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<id>urn:sha1:5444c5cafdce08e5fc575413b32678ac34163521</id>
<content type='text'>
Document RZ/Five (R9A07G043) SYSC bindings. The SYSC block found on the
RZ/Five SoC is almost identical to one found on the RZ/G2UL (and alike)
SoC's. "renesas,r9a07g043-sysc" compatible string will be used on the
RZ/Five SoC so to make this clear, update the comment to include RZ/Five
SoC.

The SYSC block on RZ/Five has no interrupts to the core so to accommodate
this SoC make interrupts{,-names} properties optional.

Signed-off-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Link: https://lore.kernel.org/r/20220722141506.20171-2-prabhakar.mahadev-lad.rj@bp.renesas.com
Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
</content>
</entry>
<entry>
<title>dt-bindings: soc: renesas: Move renesas,rzg2l-sysc from arm to soc</title>
<updated>2022-05-05T09:59:47Z</updated>
<author>
<name>Geert Uytterhoeven</name>
<email>geert+renesas@glider.be</email>
</author>
<published>2022-05-02T12:40:58Z</published>
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<id>urn:sha1:033a26dcbe10476c5203f590dce0537fac802d03</id>
<content type='text'>
The Renesas RZ/{G2L,V2L} System Controller (SYSC) DT binding is not
really a power-related DT binding, hence it does not belong under
Documentation/devicetree/bindings/power/.
Move it to Documentation/devicetree/bindings/soc/renesas/.

Signed-off-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Link: https://lore.kernel.org/r/a47015888f99476a5206a556dce93503494d9a73.1651495078.git.geert+renesas@glider.be
</content>
</entry>
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