<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/Documentation/devicetree/bindings/pinctrl, branch linux-5.1.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-5.1.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2019-02-21T12:37:19Z</updated>
<entry>
<title>dt-bindings: pinctrl: Document the i.MX50 IOMUXC binding</title>
<updated>2019-02-21T12:37:19Z</updated>
<author>
<name>Jonathan Neuschäfer</name>
<email>j.neuschaefer@gmx.net</email>
</author>
<published>2019-01-29T16:55:28Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=dcab77888da978a1853158ff86b93b5cf7f07d25'/>
<id>urn:sha1:dcab77888da978a1853158ff86b93b5cf7f07d25</id>
<content type='text'>
AFAICS from the i.MX50 Reference Manual, the i.MX50 IOMUXC works the
same as the one in i.MX51, so I copied fsl,imx51-pinctrl.txt and changed
the text to imx50.

Signed-off-by: Jonathan Neuschäfer &lt;j.neuschaefer@gmx.net&gt;
Cc: Dong Aisheng &lt;dong.aisheng@linaro.org&gt;
Cc: Shawn Guo &lt;shawn.guo@linaro.org&gt;
Reviewed-by: Fabio Estevam &lt;festevam@gmail.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: add documentation for slew rate</title>
<updated>2019-02-08T12:07:25Z</updated>
<author>
<name>Claudiu Beznea</name>
<email>claudiu.beznea@microchip.com</email>
</author>
<published>2019-02-07T09:25:08Z</published>
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<id>urn:sha1:5e07a820649bc7e29249c832abc33c1bffd0e2db</id>
<content type='text'>
Add documentation for slew rate.

Signed-off-by: Claudiu Beznea &lt;claudiu.beznea@microchip.com&gt;
Acked-by: Ludovic Desroches &lt;ludovic.desroches@microchip.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: add bindings for SAM9X60</title>
<updated>2019-02-08T12:06:40Z</updated>
<author>
<name>Claudiu Beznea</name>
<email>claudiu.beznea@microchip.com</email>
</author>
<published>2019-02-07T09:25:01Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=fde84f194aaddc3988e5cdc0c7088e5cd9683061'/>
<id>urn:sha1:fde84f194aaddc3988e5cdc0c7088e5cd9683061</id>
<content type='text'>
Add device tree binding for SAM9X60 pin controller.

Signed-off-by: Claudiu Beznea &lt;claudiu.beznea@microchip.com&gt;
Acked-by: Ludovic Desroches &lt;ludovic.desroches@microchip.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: add documentation for banks</title>
<updated>2019-02-08T12:06:16Z</updated>
<author>
<name>Claudiu Beznea</name>
<email>claudiu.beznea@microchip.com</email>
</author>
<published>2019-02-07T09:24:57Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=1d741f2e977d7783cd706d6759e29cf36be9d412'/>
<id>urn:sha1:1d741f2e977d7783cd706d6759e29cf36be9d412</id>
<content type='text'>
Add documentation for at91 pin controller banks.

Signed-off-by: Claudiu Beznea &lt;claudiu.beznea@microchip.com&gt;
Acked-by: Ludovic Desroches &lt;ludovic.desroches@microchip.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'ib-qcom-spmi' of /home/linus/linux-gpio into devel</title>
<updated>2019-01-28T13:31:13Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2019-01-28T13:31:13Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=67e436ffd648441a149308239d22e1ff46096d60'/>
<id>urn:sha1:67e436ffd648441a149308239d22e1ff46096d60</id>
<content type='text'>
</content>
</entry>
<entry>
<title>dt-bindings: imx: Add pinctrl binding doc for imx8mm</title>
<updated>2019-01-28T13:11:05Z</updated>
<author>
<name>Bai Ping</name>
<email>ping.bai@nxp.com</email>
</author>
<published>2019-01-22T10:17:13Z</published>
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<id>urn:sha1:c1c9d41319c35daa099b2e6cd1325e3ae55cfda8</id>
<content type='text'>
Add binding doc imx8mm pinctrl driver.

Signed-off-by: Bai Ping &lt;ping.bai@nxp.com&gt;
Acked-by: Aisheng Dong &lt;aisheng.dong@nxp.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>Merge branch 'ib-meson-fixes' into devel</title>
<updated>2019-01-22T09:55:07Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2019-01-22T09:55:07Z</published>
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<id>urn:sha1:fe4a6485b819560381bcd83926edd86043950cbf</id>
<content type='text'>
</content>
</entry>
<entry>
<title>dt-bindings: pinctrl: meson: update register descriptions</title>
<updated>2019-01-21T13:49:22Z</updated>
<author>
<name>Jerome Brunet</name>
<email>jbrunet@baylibre.com</email>
</author>
<published>2019-01-17T10:23:13Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=cf892f38e8568a20b853ec6efc2116c3e6e0215f'/>
<id>urn:sha1:cf892f38e8568a20b853ec6efc2116c3e6e0215f</id>
<content type='text'>
like pull-enable, pull should be optional has this region is available on
every controllers. Also, the g12a feature a new region "ds" for the
drive-strength

All this region thing is one big mess. I suspect that there is only one
big GPIO region with holes in it. All registers between the current
regions reads '0' so it is probably just spare space to handle more pins.

Since we need to continue to handle the existing controllers, switching to
one single region now would not simplify things. However, if more
organisation layouts and features keep on being added, we may have to look
at this again

Fixes: 3cd3c83f6752 ("pinctrl: Add compatibles for Amlogic Meson G12A pin controllers")
Signed-off-by: Jerome Brunet &lt;jbrunet@baylibre.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: pinctrl: qcom-pmic-gpio: add qcom,pmi8998-gpio binding</title>
<updated>2019-01-21T12:49:06Z</updated>
<author>
<name>Brian Masney</name>
<email>masneyb@onstation.org</email>
</author>
<published>2019-01-19T20:42:38Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=697818f383fc548cdbfb1528c7067994739ace04'/>
<id>urn:sha1:697818f383fc548cdbfb1528c7067994739ace04</id>
<content type='text'>
Add support for the PMI8998 GPIO variant to the Qualcomm PMIC GPIO
binding document.

Signed-off-by: Brian Masney &lt;masneyb@onstation.org&gt;
Reviewed-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
Reviewed-by: Bjorn Andersson &lt;bjorn.andersson@linaro.org&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
<entry>
<title>pinctrl: dt-bindings: Fix the armada-37xx documentation</title>
<updated>2019-01-11T08:53:59Z</updated>
<author>
<name>Gregory CLEMENT</name>
<email>gregory.clement@bootlin.com</email>
</author>
<published>2018-12-21T17:32:59Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=3fbb9a8d79a84bf549979cad5511e202098d0aaa'/>
<id>urn:sha1:3fbb9a8d79a84bf549979cad5511e202098d0aaa</id>
<content type='text'>
While it was possible to configure the PCIe1 Wakeup pin, it was missing
in the bidding, let's document it.

Signed-off-by: Gregory CLEMENT &lt;gregory.clement@bootlin.com&gt;
Tested-by: Miquel Raynal &lt;miquel.raynal@bootlin.com&gt;
Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
</content>
</entry>
</feed>
