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<title>kernel/Documentation/devicetree/bindings/media/xilinx, branch linux-4.3.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.3.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.3.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2015-04-03T04:04:18Z</updated>
<entry>
<title>[media] v4l: xilinx: Add Test Pattern Generator driver</title>
<updated>2015-04-03T04:04:18Z</updated>
<author>
<name>Laurent Pinchart</name>
<email>laurent.pinchart@ideasonboard.com</email>
</author>
<published>2013-05-15T14:36:56Z</published>
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<id>urn:sha1:a5562f65b1371a0988b707c10c44fcc2bba56990</id>
<content type='text'>
The TPG generates multiple static or dynamic test patterns. The driver
currently hardcodes the pattern to the moving box pattern.

Signed-off-by: Christian Kohn &lt;christian.kohn@xilinx.com&gt;
Signed-off-by: Hyun Kwon &lt;hyun.kwon@xilinx.com&gt;
Signed-off-by: Laurent Pinchart &lt;laurent.pinchart@ideasonboard.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Acked-by: Hans Verkuil &lt;hans.verkuil@cisco.com&gt;
Signed-off-by: Mauro Carvalho Chehab &lt;mchehab@osg.samsung.com&gt;
</content>
</entry>
<entry>
<title>[media] v4l: xilinx: Add Video Timing Controller driver</title>
<updated>2015-04-03T04:01:37Z</updated>
<author>
<name>Laurent Pinchart</name>
<email>laurent.pinchart@ideasonboard.com</email>
</author>
<published>2014-03-26T14:46:25Z</published>
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<id>urn:sha1:40ac9b196d07813132e2d5a14aae40d5812f131e</id>
<content type='text'>
The Video Timing Controller (VTC) includes a timing detector and/or a
timing generator. Only the generator is currently supported.

Signed-off-by: Laurent Pinchart &lt;laurent.pinchart@ideasonboard.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Acked-by: Hans Verkuil &lt;hans.verkuil@cisco.com&gt;
Signed-off-by: Mauro Carvalho Chehab &lt;mchehab@osg.samsung.com&gt;
</content>
</entry>
<entry>
<title>[media] v4l: xilinx: Add Xilinx Video IP core</title>
<updated>2015-04-03T03:59:49Z</updated>
<author>
<name>Laurent Pinchart</name>
<email>laurent.pinchart@ideasonboard.com</email>
</author>
<published>2013-05-15T14:36:19Z</published>
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<id>urn:sha1:df3305156f989339529b3d6744b898d498fb1f7b</id>
<content type='text'>
Xilinx platforms have no hardwired video capture or video processing
interface. Users create capture and memory to memory processing
pipelines in the FPGA fabric to suit their particular needs, by
instantiating video IP cores from a large library.

The Xilinx Video IP core is a framework that models a video pipeline
described in the device tree and expose the pipeline to userspace
through the media controller and V4L2 APIs.

Signed-off-by: Laurent Pinchart &lt;laurent.pinchart@ideasonboard.com&gt;
Signed-off-by: Hyun Kwon &lt;hyun.kwon@xilinx.com&gt;
Signed-off-by: Radhey Shyam Pandey &lt;radheys@xilinx.com&gt;
Signed-off-by: Michal Simek &lt;michal.simek@xilinx.com&gt;
Acked-by: Hans Verkuil &lt;hans.verkuil@cisco.com&gt;
Signed-off-by: Mauro Carvalho Chehab &lt;mchehab@osg.samsung.com&gt;
</content>
</entry>
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