kernel/Documentation/devicetree/bindings/mailbox, branch linux-rolling-stable

dt-bindings: Remove extra blank lines

2025-11-17T17:24:50Z

Generally at most 1 blank line is the standard style for DT schema files. Remove the few cases with more than 1 so that the yamllint check for this can be enabled. Acked-by: Lee Jones Reviewed-by: Mathieu Poirier # remoteproc Acked-by: Georgi Djakov Acked-by: Vinod Koul Acked-by: Andi Shyti Acked-by: Bartosz Golaszewski Acked-by: Jonathan Cameron Acked-by: Philipp Zabel Acked-by: Uwe Kleine-König # for allwinner,sun4i-a10-pwm.yaml Reviewed-by: Miquel Raynal # mtd Acked-by: Guenter Roeck Acked-by: Mark Brown Acked-by: Greg Kroah-Hartman Acked-by: Sebastian Reichel Acked-by: Manivannan Sadhasivam # For PCI controller bindings Link: https://patch.msgid.link/20251023143957.2899600-1-robh@kernel.org Signed-off-by: Rob Herring (Arm)

dt-bindings: Fix inconsistent quoting

2025-11-17T17:24:50Z

yamllint has gained a new check which checks for inconsistent quoting (mixed " and ' quotes within a file). Fix all the cases yamllint found so we can enable the check (once the check is in a release). As single quotes are (slightly) preferred, use them throughout the modified files even if double quotes are mostly used. Acked-by: Alexandre Belloni Reviewed-by: Krzysztof Kozlowski Acked-by: Jonathan Cameron Acked-by: Andrew Jeffery Acked-by: Jassi Brar Acked-by: Linus Walleij Acked-by: Lee Jones Acked-by: Bartosz Golaszewski Link: https://patch.msgid.link/20251015232015.846282-1-robh@kernel.org Signed-off-by: Rob Herring (Arm)

dt-bindings: mailbox: Convert apm,xgene-slimpro-mbox to DT schema

2025-10-14T22:12:15Z

Convert APM X-Gene slimpro-mbox binding to DT schema format. It's a straight-forward conversion. Signed-off-by: Rob Herring (Arm)

Merge tag 'mailbox-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox

2025-10-08T18:44:21Z

Pull mailbox updates from Jassi Brar: - Qualcomm: add Glymur CPUCP mailbox binding - Xilinx Zynq: misc cleanup - MediaTek: - add new GPUEB mailbox driver - cmdq: remove pm_runtime calls from send_data - gce: make clock-names optional - misc: - change mailbox-altera maintainer - remove redundant 'fast_io' in regmap_config - mhuv3: Remove no_free_ptr * tag 'mailbox-v6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/jassibrar/mailbox: mailbox: mtk-cmdq: Remove pm_runtime APIs from cmdq_mbox_send_data() mailbox: add MediaTek GPUEB IPI mailbox dt-bindings: mailbox: Add MT8196 GPUEB Mailbox mailbox: zynqmp-ipi: Fix SGI cleanup on unbind mailbox: zynqmp-ipi: Fix out-of-bounds access in mailbox cleanup loop mailbox: zynqmp-ipi: Remove dev.parent check in zynqmp_ipi_free_mboxes mailbox: zynqmp-ipi: Remove redundant mbox_controller_unregister() call mailbox: remove unneeded 'fast_io' parameter in regmap_config dt-bindings: mailbox: mediatek,gce-mailbox: Make clock-names optional dt-bindings: mailbox: qcom: Document Glymur CPUCP mailbox controller binding MAINTAINERS: Change mailbox-altera maintainer mailbox: arm_mhuv3: Remove no_free_ptr() to maintain the original form of the pointer

dt-bindings: mailbox: Add MT8196 GPUEB Mailbox

2025-10-06T23:14:01Z

The MediaTek MT8196 SoC includes an embedded MCU referred to as "GPUEB", acting as glue logic to control power and frequency of the Mali GPU. This MCU runs special-purpose firmware for this use, and the main application processor communicates with it through a mailbox. Add a binding that describes this mailbox. Reviewed-by: AngeloGioacchino Del Regno Acked-by: Conor Dooley Reviewed-by: Rob Herring (Arm) Signed-off-by: Nicolas Frattaroli Signed-off-by: Jassi Brar

dt-bindings: mailbox: mediatek,gce-mailbox: Make clock-names optional

2025-10-06T23:14:00Z

The GCE Mailbox needs only one clock and the clock-names can be used only by the driver (which, for instance, does not use it), and this is true for all of the currently supported MediaTek SoCs. Stop requiring to specify clock-names on all non-MT8195 GCEs. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Chen-Yu Tsai Acked-by: Rob Herring (Arm) Reviewed-by: Matthias Brugger Signed-off-by: Jassi Brar

dt-bindings: mailbox: qcom: Document Glymur CPUCP mailbox controller binding

2025-10-06T23:13:53Z

Document CPU Control Processor (CPUCP) mailbox controller for Qualcomm Glymur SoCs. It is software compatible with X1E80100 CPUCP mailbox controller hence fallback to it. Signed-off-by: Sibi Sankar Acked-by: Rob Herring (Arm) Signed-off-by: Jassi Brar

Merge tag 'riscv-for-linus-6.18-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux

2025-10-04T17:36:22Z

Pull more RISC-V updates from Paul Walmsley: - Support for the RISC-V-standardized RPMI interface. RPMI is a platform management communication mechanism between OSes running on application processors, and a remote platform management processor. Similar to ARM SCMI, TI SCI, etc. This includes irqchip, mailbox, and clk changes. - Support for the RISC-V-standardized MPXY SBI extension. MPXY is a RISC-V-specific standard implementing a shared memory mailbox between S-mode operating systems (e.g., Linux) and M-mode firmware (e.g., OpenSBI). It is part of this PR since one of its use cases is to enable M-mode firmware to act as a single RPMI client for all RPMI activity on a core (including S-mode RPMI activity). Includes a mailbox driver. - Some ACPI-related updates to enable the use of RPMI and MPXY. - The addition of Linux-wide memcpy_{from,to}_le32() static inline functions, for RPMI use. - An ACPI Kconfig change to enable boot logos on any ACPI-using architecture (including RISC-V) - A RISC-V defconfig change to add GPIO keyboard and event device support, for front panel shutdown or reboot buttons * tag 'riscv-for-linus-6.18-mw2' of git://git.kernel.org/pub/scm/linux/kernel/git/riscv/linux: (26 commits) clk: COMMON_CLK_RPMI should depend on RISCV ACPI: support BGRT table on RISC-V MAINTAINERS: Add entry for RISC-V RPMI and MPXY drivers RISC-V: Enable GPIO keyboard and event device in RV64 defconfig irqchip/riscv-rpmi-sysmsi: Add ACPI support mailbox/riscv-sbi-mpxy: Add ACPI support irqchip/irq-riscv-imsic-early: Export imsic_acpi_get_fwnode() ACPI: RISC-V: Add RPMI System MSI to GSI mapping ACPI: RISC-V: Add support to update gsi range ACPI: RISC-V: Create interrupt controller list in sorted order ACPI: scan: Update honor list for RPMI System MSI ACPI: Add support for nargs_prop in acpi_fwnode_get_reference_args() ACPI: property: Refactor acpi_fwnode_get_reference_args() to support nargs_prop irqchip: Add driver for the RPMI system MSI service group dt-bindings: Add RPMI system MSI interrupt controller bindings dt-bindings: Add RPMI system MSI message proxy bindings clk: Add clock driver for the RISC-V RPMI clock service group dt-bindings: clock: Add RPMI clock service controller bindings dt-bindings: clock: Add RPMI clock service message proxy bindings mailbox: Add RISC-V SBI message proxy (MPXY) based mailbox driver ...

Merge tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc

2025-10-02T00:32:51Z

Pull SoC driver updates from Arnd Bergmann: "Lots of platform specific updates for Qualcomm SoCs, including a new TEE subsystem driver for the Qualcomm QTEE firmware interface. Added support for the Apple A11 SoC in drivers that are shared with the M1/M2 series, among more updates for those. Smaller platform specific driver updates for Renesas, ASpeed, Broadcom, Nvidia, Mediatek, Amlogic, TI, Allwinner, and Freescale SoCs. Driver updates in the cache controller, memory controller and reset controller subsystems. SCMI firmware updates to add more features and improve robustness. This includes support for having multiple SCMI providers in a single system. TEE subsystem support for protected DMA-bufs, allowing hardware to access memory areas that managed by the kernel but remain inaccessible from the CPU in EL1/EL0" * tag 'soc-drivers-6.18' of git://git.kernel.org/pub/scm/linux/kernel/git/soc/soc: (139 commits) soc/fsl/qbman: Use for_each_online_cpu() instead of for_each_cpu() soc: fsl: qe: Drop legacy-of-mm-gpiochip.h header from GPIO driver soc: fsl: qe: Change GPIO driver to a proper platform driver tee: fix register_shm_helper() pmdomain: apple: Add "apple,t8103-pmgr-pwrstate" dt-bindings: spmi: Add Apple A11 and T2 compatible serial: qcom-geni: Load UART qup Firmware from linux side spi: geni-qcom: Load spi qup Firmware from linux side i2c: qcom-geni: Load i2c qup Firmware from linux side soc: qcom: geni-se: Add support to load QUP SE Firmware via Linux subsystem soc: qcom: geni-se: Cleanup register defines and update copyright dt-bindings: qcom: se-common: Add QUP Peripheral-specific properties for I2C, SPI, and SERIAL bus Documentation: tee: Add Qualcomm TEE driver tee: qcom: enable TEE_IOC_SHM_ALLOC ioctl tee: qcom: add primordial object tee: add Qualcomm TEE driver tee: increase TEE_MAX_ARG_SIZE to 4096 tee: add TEE_IOCTL_PARAM_ATTR_TYPE_OBJREF tee: add TEE_IOCTL_PARAM_ATTR_TYPE_UBUF tee: add close_context to TEE driver operation ...

dt-bindings: mailbox: mediatek,gce-mailbox: Make clock-names optional

2025-09-26T19:50:44Z

The GCE Mailbox needs only one clock and the clock-names can be used only by the driver (which, for instance, does not use it), and this is true for all of the currently supported MediaTek SoCs. Stop requiring to specify clock-names on all non-MT8195 GCEs. Signed-off-by: AngeloGioacchino Del Regno Reviewed-by: Matthias Brugger Acked-by: Rob Herring (Arm) Reviewed-by: Chen-Yu Tsai Signed-off-by: Rob Herring (Arm)