<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/Documentation/devicetree/bindings/interrupt-controller/arm,gic-v3.yaml, branch linux-6.2.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.2.y</id>
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<updated>2023-02-02T23:10:58Z</updated>
<entry>
<title>dt-bindings: interrupt-controller: arm,gic-v3: Fix typo in description of msi-controller property</title>
<updated>2023-02-02T23:10:58Z</updated>
<author>
<name>Lad Prabhakar</name>
<email>prabhakar.csengg@gmail.com</email>
</author>
<published>2023-01-30T23:43:35Z</published>
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<id>urn:sha1:707344c8a188bb1d6704d3546229fc7a07c01a63</id>
<content type='text'>
Fix typo functionnality -&gt; functionality.

Signed-off-by: Lad Prabhakar &lt;prabhakar.csengg@gmail.com&gt;
Link: https://lore.kernel.org/r/20230130234335.13952-1-prabhakar.csengg@gmail.com
Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: interrupt-controller: arm,gic-v3: Make 'interrupts' optional</title>
<updated>2022-08-23T15:41:21Z</updated>
<author>
<name>Jean-Philippe Brucker</name>
<email>jean-philippe@linaro.org</email>
</author>
<published>2022-08-22T15:22:23Z</published>
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<id>urn:sha1:92572a8ec3d8b4dc186eeefa1c973645c0753ae0</id>
<content type='text'>
A GICv3 implementation without virtualization, such as the base QEMU
virt machine (without -M virtualization=on), does not issue maintenance
interrupts. Therefore its device-tree node does not need an 'interrupts'
property. Currently, validating the QEMU virt device-tree throws a
warning that 'interrupts' is missing. Make it optional.

Signed-off-by: Jean-Philippe Brucker &lt;jean-philippe@linaro.org&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Acked-by: Marc Zyngier &lt;maz@kernel.org&gt;
Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
Link: https://lore.kernel.org/r/20220822152224.507497-3-jean-philippe@linaro.org
</content>
</entry>
<entry>
<title>dt-bindings: interrupt-controller: arm,gic-v3: Make the v2 compat requirements explicit</title>
<updated>2022-05-04T14:43:12Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2022-04-09T10:16:17Z</published>
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<id>urn:sha1:4053b6b43fae126bea0654493fe512d364ee9fc1</id>
<content type='text'>
A common mistake when writing a device tree for a platform that is using
GICv3 with ancient CPUs is to overlook the MMIO frames that implement
the GICv2 compatibility feature, because this feature is implemented by
the CPUs and not by the GIC itself.

The compatibility feature itself is optional (all the modern
implementations have dropped it), but is present in all the ARM Ltd
implementations of the ARMv8.0 architecture (A3x, A53, A57, A72, A73),
and many others from various implementers.

Make it explicit that GICC, GICH and GICV are required for these CPUs.
Also take this opportunity to update my email address, as people keep
sending them to the wrong place...

Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Cc: Rob Herring &lt;robh+dt@kernel.org&gt;
Cc: Krzysztof Kozlowski &lt;krzk+dt@kernel.org&gt;
Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Link: https://lore.kernel.org/r/20220409101617.268796-1-maz@kernel.org
</content>
</entry>
<entry>
<title>dt-bindings: Improve phandle-array schemas</title>
<updated>2022-02-04T15:43:42Z</updated>
<author>
<name>Rob Herring</name>
<email>robh@kernel.org</email>
</author>
<published>2022-01-19T01:50:38Z</published>
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<id>urn:sha1:39bd2b6a3783b8990d97494ec4c8698ba5bb6740</id>
<content type='text'>
The 'phandle-array' type is a bit ambiguous. It can be either just an
array of phandles or an array of phandles plus args. Many schemas for
phandle-array properties aren't clear in the schema which case applies
though the description usually describes it.

The array of phandles case boils down to needing:

items:
  maxItems: 1

The phandle plus args cases should typically take this form:

items:
  - items:
      - description: A phandle
      - description: 1st arg cell
      - description: 2nd arg cell

With this change, some examples need updating so that the bracketing of
property values matches the schema.

Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
Acked-by: Viresh Kumar &lt;viresh.kumar@linaro.org&gt;
Acked-by: Vinod Koul &lt;vkoul@kernel.org&gt;
Acked-by: Ulf Hansson &lt;ulf.hansson@linaro.org&gt;
Acked-by: Georgi Djakov &lt;djakov@kernel.org&gt;
Reviewed-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Acked-by: Mark Brown &lt;broonie@kernel.org&gt;
Acked-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@canonical.com&gt;
Acked-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
Acked-by: Greg Kroah-Hartman &lt;gregkh@linuxfoundation.org&gt;
Acked-by: Marc Kleine-Budde &lt;mkl@pengutronix.de&gt;
Link: https://lore.kernel.org/r/20220119015038.2433585-1-robh@kernel.org
</content>
</entry>
<entry>
<title>dt-bindings: interrupt-controller: arm,gic-v3: Fix 'interrupts' cell size in example</title>
<updated>2022-01-11T17:54:35Z</updated>
<author>
<name>Rob Herring</name>
<email>robh@kernel.org</email>
</author>
<published>2022-01-06T18:25:13Z</published>
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<id>urn:sha1:e3a3356d1745befbe62b9f0ada1a38f10a54ff2a</id>
<content type='text'>
The 2nd example has an interrupts cells size of 4, but the 'interrupts'
property has 3 cells. The example should also be separate since the cell
size differs in each example.

Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
Acked-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20220106182518.1435497-5-robh@kernel.org
</content>
</entry>
<entry>
<title>dt-bindings: interrupt-controller: arm,gic-v3: Describe GICv3 optional properties</title>
<updated>2021-06-11T13:26:31Z</updated>
<author>
<name>Lad Prabhakar</name>
<email>prabhakar.mahadev-lad.rj@bp.renesas.com</email>
</author>
<published>2021-06-09T15:51:08Z</published>
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<id>urn:sha1:4e08a559a18c1b6424e56859c74adb4b29c17318</id>
<content type='text'>
Describe the optional GICv3 properties:
- clocks
- clock-names
- power-domains
- resets

Signed-off-by: Lad Prabhakar &lt;prabhakar.mahadev-lad.rj@bp.renesas.com&gt;
Reviewed-by: Biju Das &lt;biju.das.jz@bp.renesas.com&gt;
Reviewed-by: Geert Uytterhoeven &lt;geert+renesas@glider.be&gt;
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
Link: https://lore.kernel.org/r/20210609155108.16590-1-prabhakar.mahadev-lad.rj@bp.renesas.com
</content>
</entry>
<entry>
<title>dt-bindings: Remove cases of 'allOf' containing a '$ref'</title>
<updated>2020-05-03T16:10:41Z</updated>
<author>
<name>Rob Herring</name>
<email>robh@kernel.org</email>
</author>
<published>2020-04-16T00:55:49Z</published>
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<id>urn:sha1:3d21a46093352f7802b9c66c7cce35cd02a50e53</id>
<content type='text'>
json-schema versions draft7 and earlier have a weird behavior in that
any keywords combined with a '$ref' are ignored (silently). The correct
form was to put a '$ref' under an 'allOf'. This behavior is now changed
in the 2019-09 json-schema spec and '$ref' can be mixed with other
keywords. The json-schema library doesn't yet support this, but the
tooling now does a fixup for this and either way works.

This has been a constant source of review comments, so let's change this
treewide so everyone copies the simpler syntax.

Scripted with ruamel.yaml with some manual fixups. Some minor whitespace
changes from the script.

Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
Acked-by: Maxime Ripard &lt;mripard@kernel.org&gt;
Acked-by: Lee Jones &lt;lee.jones@linaro.org&gt;
Acked-By: Vinod Koul &lt;vkoul@kernel.org&gt;
Acked-by: Mark Brown &lt;broonie@kernel.org&gt;
Acked-by: Alexandre Belloni &lt;alexandre.belloni@bootlin.com&gt;
Acked-by: Wolfram Sang &lt;wsa@the-dreams.de&gt; # for I2C
Reviewed-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Acked-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt; #for-iio
Reviewed-by: Stephen Boyd &lt;sboyd@kernel.org&gt; # clock
Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: interrupt-controller: arm,gic-v3: Add missing type to interrupt-partition-* nodes</title>
<updated>2019-11-26T19:29:33Z</updated>
<author>
<name>Rob Herring</name>
<email>robh@kernel.org</email>
</author>
<published>2019-11-21T23:06:47Z</published>
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<id>urn:sha1:cf7d88fb867c107a6b93c8a180ce9831fd4dc6fb</id>
<content type='text'>
Add missing 'type: object' schema to interrupt-partition-* nodes. Found
with fix to meta-schema checks.

Cc: Thomas Gleixner &lt;tglx@linutronix.de&gt;
Cc: Jason Cooper &lt;jason@lakedaemon.net&gt;
Acked-by: Marc Zyngier &lt;maz@kernel.org&gt;
Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: interrupt-controller: arm,gic-v3: Describe EPPI range support</title>
<updated>2019-08-20T09:23:35Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2019-07-18T12:18:51Z</published>
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<id>urn:sha1:4b049063e0bcbfd302f6bf867de9d55a965d622e</id>
<content type='text'>
Update the GICv3 binding to allow interrupts in the EPPI range.

Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: interrupt-controller: arm,gic-v3: Describe ESPI range support</title>
<updated>2019-08-20T09:04:09Z</updated>
<author>
<name>Marc Zyngier</name>
<email>maz@kernel.org</email>
</author>
<published>2019-07-16T14:18:40Z</published>
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<id>urn:sha1:866246534836c60f706076cdefcd45072ad9eab2</id>
<content type='text'>
GICv3.1 introduces support for new interrupt ranges, one of them being
the Extended SPI range (ESPI). The DT binding is extended to deal with
it as a new interrupt class.

Reviewed-by: Lokesh Vutla &lt;lokeshvutla@ti.com&gt;
Signed-off-by: Marc Zyngier &lt;maz@kernel.org&gt;
</content>
</entry>
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