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<title>kernel/Documentation/devicetree/bindings/display/tegra, branch linux-6.2.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.2.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.2.y'/>
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<updated>2022-10-20T14:21:07Z</updated>
<entry>
<title>dt-bindings: Remove "status" from schema examples, again</title>
<updated>2022-10-20T14:21:07Z</updated>
<author>
<name>Rob Herring</name>
<email>robh@kernel.org</email>
</author>
<published>2022-10-14T20:51:04Z</published>
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<id>urn:sha1:c9adc3bd1180d2911d2b1b886dbec916805be998</id>
<content type='text'>
There's no reason to have "status" properties in examples. "okay" is the
default, and "disabled" turns off some schema checks ('required'
specifically).

A meta-schema check for this is pending, so hopefully the last time to
fix these.

Fix the indentation in intel,phy-thunderbay-emmc while we're here.

Acked-by: Nicolas Ferre &lt;nicolas.ferre@microchip.com&gt;
Acked-by: Thierry Reding &lt;treding@nvidia.com&gt;
Acked-by: Jonathan Cameron &lt;Jonathan.Cameron@huawei.com&gt; #for-iio
Reviewed-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Acked-By: Vinod Koul &lt;vkoul@kernel.org&gt;
Link: https://lore.kernel.org/r/20221014205104.2822159-1-robh@kernel.org
Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: display: drop minItems equal to maxItems</title>
<updated>2022-08-29T19:58:17Z</updated>
<author>
<name>Krzysztof Kozlowski</name>
<email>krzysztof.kozlowski@linaro.org</email>
</author>
<published>2022-08-25T11:33:34Z</published>
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<id>urn:sha1:71667902e5386dd974a0d14deb51f92d0949b47a</id>
<content type='text'>
minItems, if missing, are implicitly equal to maxItems, so drop
redundant piece to reduce size of code.

Signed-off-by: Krzysztof Kozlowski &lt;krzysztof.kozlowski@linaro.org&gt;
Reviewed-by: Alim Akhtar &lt;alim.akhtar@samsung.com&gt;
Reviewed-by: Dmitry Baryshkov &lt;dmitry.baryshkov@linaro.org&gt;
Reviewed-by: Laurent Pinchart &lt;laurent.pinchart+renesas@ideasonboard.com&gt;
Link: https://lore.kernel.org/r/20220825113334.196908-5-krzysztof.kozlowski@linaro.org
Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: host1x: Fix bracketing in example</title>
<updated>2022-07-08T14:27:52Z</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2022-06-27T14:19:56Z</published>
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<id>urn:sha1:a72d4b182f4e092573035fe6fa9402a14111fd64</id>
<content type='text'>
The bracketing for the interrupts property in the device tree
example is incorrect. Fix it.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: Add bindings for Tegra234 Host1x and VIC</title>
<updated>2022-07-08T14:27:52Z</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2022-06-27T14:19:55Z</published>
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<id>urn:sha1:5c5a6ff72e193302b21fd4c2afc6bd8cc26f68e2</id>
<content type='text'>
Update VIC and Host1x bindings for changes in Tegra234.

Namely,
- New compatible strings
- Sharded syncpoint interrupts
- Optional reset.

Also, fix the order of descriptions for VM/hypervisor
register apertures -- while the reg-names specification
was correct, the descriptions for these were switched.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: host1x: Add iommu-map property</title>
<updated>2022-07-08T13:54:52Z</updated>
<author>
<name>Mikko Perttunen</name>
<email>mperttunen@nvidia.com</email>
</author>
<published>2022-06-27T14:19:47Z</published>
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<id>urn:sha1:ea1a6270ff4fa4460914cf788b0560271a577615</id>
<content type='text'>
Add schema information for specifying context stream IDs. This uses
the standard iommu-map property.

Signed-off-by: Mikko Perttunen &lt;mperttunen@nvidia.com&gt;
Reviewed-by: Robin Murphy &lt;robin.murphy@arm.com&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: display: tegra: Convert to json-schema</title>
<updated>2022-07-07T16:30:00Z</updated>
<author>
<name>Thierry Reding</name>
<email>treding@nvidia.com</email>
</author>
<published>2020-05-25T15:32:08Z</published>
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<id>urn:sha1:fe8b45aa61153f44a2e4851b021fda0b8bc94fb9</id>
<content type='text'>
Convert the Tegra host1x controller bindings from the free-form text
format to json-schema.

This also adds the missing display-hub DT bindings that were not
previously documented.

Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: host1x: Document Memory Client resets of Host1x, GR2D and GR3D</title>
<updated>2021-12-17T13:58:06Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2021-11-30T23:23:14Z</published>
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<id>urn:sha1:0c41e287f7541aee58c5a0c4437524fbdbf63bd9</id>
<content type='text'>
Memory Client should be blocked before hardware reset is asserted in order
to prevent memory corruption and hanging of memory controller.

Document Memory Client resets of Host1x, GR2D and GR3D hardware units.

Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>dt-bindings: host1x: Document OPP and power domain properties</title>
<updated>2021-12-17T13:58:05Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2021-11-30T23:23:13Z</published>
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<id>urn:sha1:425a68a963698867a9b6a8d82fcd41354a01f0ab</id>
<content type='text'>
Document new DVFS OPP table and power domain properties of the Host1x bus
and devices sitting on the bus.

Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Signed-off-by: Thierry Reding &lt;treding@nvidia.com&gt;
</content>
</entry>
<entry>
<title>media: dt-bindings: tegra: Update csi data-lanes to maximum 8 lanes</title>
<updated>2021-01-04T12:02:44Z</updated>
<author>
<name>Sowjanya Komatineni</name>
<email>skomatineni@nvidia.com</email>
</author>
<published>2020-12-11T17:02:40Z</published>
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<id>urn:sha1:f8c9dd2b826d8f1c23b8e86d5e4135a668a7bdd4</id>
<content type='text'>
Tegra VI/CSI hardware don't have native 8 lane CSI RX port.

But x8 capture can be supported by using consecutive x4 ports
simultaneously with HDMI-to-CSI bridges where source image is split
on to two x4 ports.

This patch updates dt-bindings for csi endpoint data-lane property
with maximum of 8 lanes.

Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Acked-by: Sakari Ailus &lt;sakari.ailus@linux.intel.com&gt;
Signed-off-by: Sowjanya Komatineni &lt;skomatineni@nvidia.com&gt;
Signed-off-by: Hans Verkuil &lt;hverkuil-cisco@xs4all.nl&gt;
Signed-off-by: Mauro Carvalho Chehab &lt;mchehab+huawei@kernel.org&gt;
</content>
</entry>
<entry>
<title>dt-bindings: host1x: Document new interconnect properties</title>
<updated>2020-11-06T18:37:20Z</updated>
<author>
<name>Dmitry Osipenko</name>
<email>digetx@gmail.com</email>
</author>
<published>2020-11-04T16:48:52Z</published>
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<id>urn:sha1:c553bb54a486eab2b0d3671db4b985c8d1ba51e9</id>
<content type='text'>
Most of Host1x devices have at least one memory client. These clients
are directly connected to the memory controller. The new interconnect
properties represent the memory client's connection to the memory
controller.

Signed-off-by: Dmitry Osipenko &lt;digetx@gmail.com&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Link: https://lore.kernel.org/r/20201104164923.21238-17-digetx@gmail.com
Signed-off-by: Krzysztof Kozlowski &lt;krzk@kernel.org&gt;
</content>
</entry>
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