<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/Documentation/devicetree/bindings/clock/mvebu-core-clock.txt, branch linux-6.2.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.2.y</id>
<link rel='self' href='https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.2.y'/>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/'/>
<updated>2019-06-25T21:35:10Z</updated>
<entry>
<title>dt-bindings: clock: mvebu: Add compatible string for 98dx1135 core clock</title>
<updated>2019-06-25T21:35:10Z</updated>
<author>
<name>Chris Packham</name>
<email>chris.packham@alliedtelesis.co.nz</email>
</author>
<published>2019-06-17T21:54:56Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=9a042e718fc0faf77db35a8106c8ded948971219'/>
<id>urn:sha1:9a042e718fc0faf77db35a8106c8ded948971219</id>
<content type='text'>
Add compatible string for the core clock on the 98dx1135 switch with
integrated CPU.

Signed-off-by: Chris Packham &lt;chris.packham@alliedtelesis.co.nz&gt;
Reviewed-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Signed-off-by: Stephen Boyd &lt;sboyd@kernel.org&gt;
</content>
</entry>
<entry>
<title>ARM: dts: mvebu: Move mv98dx3236 clock bindings</title>
<updated>2017-03-08T08:52:54Z</updated>
<author>
<name>Chris Packham</name>
<email>chris.packham@alliedtelesis.co.nz</email>
</author>
<published>2017-02-16T08:50:40Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=b4bcfccb2cecb9df1fc8860288e6356ef5c1c2f3'/>
<id>urn:sha1:b4bcfccb2cecb9df1fc8860288e6356ef5c1c2f3</id>
<content type='text'>
Previously the coreclk binding for the 98dx3236 SoC was inherited from
the armada-370/xp. This block is present in as much as it is possible to
read from the register location without causing any harm. However the
actual sampled at reset values are reflected in the DFX block.

Moving the binding to the DFX block enables support for different clock
strapping options in hardware.

Signed-off-by: Chris Packham &lt;chris.packham@alliedtelesis.co.nz&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Signed-off-by: Gregory CLEMENT &lt;gregory.clement@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>clk: mvebu: Add clk support for the orion5x SoC mv88f5181</title>
<updated>2016-09-21T09:49:09Z</updated>
<author>
<name>Jamie Lentin</name>
<email>jm@lentin.co.uk</email>
</author>
<published>2016-05-19T21:38:23Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=57d0ee077af5621102b3d1a0a701150b56e9747c'/>
<id>urn:sha1:57d0ee077af5621102b3d1a0a701150b56e9747c</id>
<content type='text'>
Referring to the u-boot sources for the Netgear WNR854T, add support
for the mv88f5181.

[gregory.clement@free-electrons.com: fix commit title]
Signed-off-by: Jamie Lentin &lt;jm@lentin.co.uk&gt;
Reviewed-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Acked-by: Rob Herring &lt;robh@kernel.org&gt;
Acked-by: Stephen Boyd &lt;sboyd@codeaurora.org&gt;
Signed-off-by: Gregory CLEMENT &lt;gregory.clement@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>devicetree: bindings: update DT bindings for Marvell EBU clock support</title>
<updated>2015-03-04T14:18:43Z</updated>
<author>
<name>Thomas Petazzoni</name>
<email>thomas.petazzoni@free-electrons.com</email>
</author>
<published>2015-03-03T14:41:05Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=9baf96886780c3ec137350da3c6418c825b2dd0a'/>
<id>urn:sha1:9baf96886780c3ec137350da3c6418c825b2dd0a</id>
<content type='text'>
With the introduction of the Marvell Armada 39x SoC, the DT bindings
for Marvell EBU clocks need to be extended. This commit include the
corresponding update to the Device Tree bindings documentation.

Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
Signed-off-by: Gregory CLEMENT &lt;gregory.clement@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>clk: mvebu: add Orion5x clock driver</title>
<updated>2014-04-26T01:03:55Z</updated>
<author>
<name>Thomas Petazzoni</name>
<email>thomas.petazzoni@free-electrons.com</email>
</author>
<published>2014-04-22T21:26:08Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=66ecbfea762ad28bd108db76775483b491068b92'/>
<id>urn:sha1:66ecbfea762ad28bd108db76775483b491068b92</id>
<content type='text'>
This commit adds a core clock driver for the Orion5x SoC, with support
for the tclk, the CPU frequency and the DDR frequency. All the details
about the Sample-At-Reset register were extracted from the U-Boot
sources for Orion5x.

Note that Orion5x does not have gatable clocks, so this core clock
driver is sufficient to support clocking on Orion5x platforms.

Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
Acked-by: Sebastian Hesselbarth &lt;sebastian.hesselbarth@gmail.com&gt;
Link: https://lkml.kernel.org/r/1398202002-28530-5-git-send-email-thomas.petazzoni@free-electrons.com
Cc: Mike Turquette &lt;mturquette@linaro.org&gt;
Signed-off-by: Jason Cooper &lt;jason@lakedaemon.net&gt;
</content>
</entry>
<entry>
<title>dt: Update binding information for mvebu core clocks with Armada 380/385</title>
<updated>2014-02-17T02:34:07Z</updated>
<author>
<name>Thomas Petazzoni</name>
<email>thomas.petazzoni@free-electrons.com</email>
</author>
<published>2014-02-10T17:32:48Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=3e8947aeba06d8cf59a6193d88ebaf02b5144f5f'/>
<id>urn:sha1:3e8947aeba06d8cf59a6193d88ebaf02b5144f5f</id>
<content type='text'>
Add the binding information for the core clocks of the Armada 380 and
Armada 385 SoCs

Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
Signed-off-by: Gregory CLEMENT &lt;gregory.clement@free-electrons.com&gt;
Signed-off-by: Jason Cooper &lt;jason@lakedaemon.net&gt;
</content>
</entry>
<entry>
<title>dt: Update binding information for mvebu core clocks with Armada 375</title>
<updated>2014-02-17T02:34:02Z</updated>
<author>
<name>Gregory CLEMENT</name>
<email>gregory.clement@free-electrons.com</email>
</author>
<published>2014-02-10T17:32:45Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=dc04f2b2f7700c5f7a2a8978cdf97015a1e60902'/>
<id>urn:sha1:dc04f2b2f7700c5f7a2a8978cdf97015a1e60902</id>
<content type='text'>
Add the binding information for the core clocks of the Armada 375 SoCs

Signed-off-by: Gregory CLEMENT &lt;gregory.clement@free-electrons.com&gt;
Reviewed-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
Signed-off-by: Jason Cooper &lt;jason@lakedaemon.net&gt;
</content>
</entry>
<entry>
<title>clk: mvebu: add mvebu core clocks.</title>
<updated>2012-11-20T13:34:08Z</updated>
<author>
<name>Sebastian Hesselbarth</name>
<email>sebastian.hesselbarth@gmail.com</email>
</author>
<published>2012-11-17T14:22:22Z</published>
<link rel='alternate' type='text/html' href='https://universe.0xinfinity.dev/distro/kernel/commit/?id=97fa4cf442ff2872000d9110686371775795a32b'/>
<id>urn:sha1:97fa4cf442ff2872000d9110686371775795a32b</id>
<content type='text'>
This driver allows to provide DT clocks for core clocks found on
Marvell Kirkwood, Dove &amp; 370/XP SoCs. The core clock frequencies and
ratios are determined by decoding the Sample-At-Reset registers.

Although technically correct, using a divider of 0 will lead to
div_by_zero panic. Let's use a ratio of 0/1 instead to fail later
with a zero clock.

Signed-off-by: Gregory CLEMENT &lt;gregory.clement@free-electrons.com&gt;
Signed-off-by: Sebastian Hesselbarth &lt;sebastian.hesselbarth@gmail.com&gt;
Signed-off-by: Andrew Lunn &lt;andrew@lunn.ch&gt;
Tested-by Gregory CLEMENT &lt;gregory.clement@free-electrons.com&gt;
</content>
</entry>
</feed>
