kernel/Documentation/devicetree/bindings/clock/microchip,mpfs-ccc.yaml, branch linux-6.2.yHosts the 0x221E linux distro kernel.https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-6.2.y2022-09-14T07:57:07Zdt-bindings: clk: document PolarFire SoC fabric clocks2022-09-14T07:57:07ZConor Dooleyconor.dooley@microchip.com2022-09-08T14:36:49Zurn:sha1:3ffb5ad24d0064f923ed30ad37e33e56eee31f2b
On PolarFire SoC there are 4 PLL/DLL blocks, located in each of the
ordinal corners of the chip, which our documentation refers to as
"Clock Conditioning Circuitry". PolarFire SoC is an FPGA, these are
highly configurable & many of the input clocks are optional.
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
Signed-off-by: Claudiu Beznea <claudiu.beznea@microchip.com>
Link: https://lore.kernel.org/r/20220908143651.1252601-3-conor.dooley@microchip.com