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<title>kernel/Documentation/devicetree/bindings/arm/omap, branch linux-4.3.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.3.y</id>
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<updated>2015-07-21T10:58:26Z</updated>
<entry>
<title>ARM: dts: Add phyBOARD-WEGA-AM335x rdk</title>
<updated>2015-07-21T10:58:26Z</updated>
<author>
<name>Teresa Remmet</name>
<email>t.remmet@phytec.de</email>
</author>
<published>2015-07-16T08:30:49Z</published>
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<id>urn:sha1:36bd1683559e23d4032defadbfbd3ccd5601b8c8</id>
<content type='text'>
phyBOARD-WEGA-AM335x represents a direct soldered
combination of a phyCORE-AM335x SoM and carrier board.

Different kind of SoM options can be connected to
the wega carrier board. So we created a separate
wega dtsi file. The final dts contains the actual
SoM on the carrier board.

WEGA carrier board features:
* ETH phy on carrier board: 1x MII
* 1x CAN
* 2x UART
* USB0 (device)
* USB1 (host)
* mSD slot

Signed-off-by: Teresa Remmet &lt;t.remmet@phytec.de&gt;
Signed-off-by: Tony Lindgren &lt;tony@atomide.com&gt;
</content>
</entry>
<entry>
<title>bus: omap_l3_noc: Fix master id address decoding for OMAP5</title>
<updated>2015-05-04T17:21:01Z</updated>
<author>
<name>Suman Anna</name>
<email>s-anna@ti.com</email>
</author>
<published>2015-04-24T17:54:20Z</published>
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<id>urn:sha1:e7309c2673a389a495fcfad70376d3bae8b9bc89</id>
<content type='text'>
The L3 Error handling on OMAP5 for the most part is very similar
to that of OMAP4, and had leveraged common data structures and
register layout definitions so far. Upon closer inspection, there
are a few minor differences causing an incorrect decoding and
reporting of the master NIU upon an error:

  1. The L3_TARG_STDERRLOG_MSTADDR.STDERRLOG_MSTADDR occupies
     11 bits on OMAP5 as against 8 bits on OMAP4, with the master
     NIU connID encoded in the 6 MSBs of the STDERRLOG_MSTADDR
     field.
  2. The CLK3 FlagMux component has 1 input source on OMAP4 and 3
     input sources on OMAP5. The common DEBUGSS source is at a
     different input on each SoC.

Fix the above issues by using a OMAP5-specific compatible property
and using SoC-specific data where there are differences.

Signed-off-by: Suman Anna &lt;s-anna@ti.com&gt;
Acked-by: Nishanth Menon &lt;nm@ti.com&gt;
Signed-off-by: Tony Lindgren &lt;tony@atomide.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc</title>
<updated>2015-04-22T16:24:55Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2015-04-22T16:24:55Z</published>
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<id>urn:sha1:8b3c8ba3d8c2680dab5363a80c024965cac08b1e</id>
<content type='text'>
Pull ARM SoC late changes from Olof Johansson:
 "We were expecting to sit on this branch through most of the merge
  window since the contents was merged into our tree late, but we ended
  up sitting on all of our contents so it can go in with the rest.

  The contents here is:

   - a large branch of cleanups of the CM/PRM blocks on OMAP.

   - a couple of patches plumbing up CM/PRM on OMAP5 and DRA7.

   - a branch with DT updates for Freescale i.MX.  including some
     shuffling from .dts to .dtsi (include) files that causes a little
     churn"

* tag 'armsoc-late' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc: (78 commits)
  ARM: OMAP2+: Fix booting with configs that don't have MFD_SYSCON
  ARM: OMAP4+: control: add support for initializing control module via DT
  ARM: dts: dra7: add minimal l4 bus layout with control module support
  ARM: dts: omap5: add minimal l4 bus layout with control module support
  ARM: OMAP4+: control: remove support for legacy pad read/write
  ARM: OMAP4: display: convert display to use syscon for dsi muxing
  ARM: dts: omap4: add minimal l4 bus layout with control module support
  ARM: dts: am4372: add minimal l4 bus layout with control module support
  ARM: dts: am43xx-epos-evm: fix pinmux node layout
  ARM: dts: am33xx: add minimal l4 bus layout with control module support
  ARM: dts: omap3: add minimal l4 bus layout with control module support
  ARM: dts: omap24xx: add minimal l4 bus layout with control module support
  ARM: OMAP2+: control: add syscon support for register accesses
  ARM: OMAP2+: id: cache omap_type value
  ARM: OMAP2+: control: remove API for getting control module base address
  ARM: OMAP2+: clock: add low-level support for regmap
  ARM: OMAP4+: PRM: get rid of cpu_is_omap44xx calls from interrupt init
  ARM: OMAP4+: PRM: setup prm_features from the PRM init time flags
  ARM: OMAP2+: CM: move SoC specific init calls within a generic API
  ARM: OMAP4+: PRM: determine prm_device_inst based on DT compatibility
  ...
</content>
</entry>
<entry>
<title>ARM: dts: dra7: add minimal l4 bus layout with control module support</title>
<updated>2015-03-31T18:26:59Z</updated>
<author>
<name>Tero Kristo</name>
<email>t-kristo@ti.com</email>
</author>
<published>2015-02-12T09:37:13Z</published>
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<id>urn:sha1:d919501feffa8715147582c3ffce96fad0c7016f</id>
<content type='text'>
This patch creates the l4_cfg and l4_wkup interconnects for DRA7, and
moves some of the generic peripherals under it. System control module
support is added to the device tree also, and the existing SCM related
functionality is moved under it.

Signed-off-by: Tero Kristo &lt;t-kristo@ti.com&gt;
</content>
</entry>
<entry>
<title>ARM: dts: omap5: add minimal l4 bus layout with control module support</title>
<updated>2015-03-31T18:26:58Z</updated>
<author>
<name>Tero Kristo</name>
<email>t-kristo@ti.com</email>
</author>
<published>2015-02-12T09:35:29Z</published>
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<id>urn:sha1:ed8509edddebf27e6e69f10c9c314f31ac4f2831</id>
<content type='text'>
This patch creates the l4_cfg and l4_wkup interconnects for OMAP5, and
moves some of the generic peripherals under it. System control module
support is added to the device tree also, and the existing SCM related
functionality is moved under it.

Signed-off-by: Tero Kristo &lt;t-kristo@ti.com&gt;
</content>
</entry>
<entry>
<title>ARM: dts: omap4: add minimal l4 bus layout with control module support</title>
<updated>2015-03-31T18:26:56Z</updated>
<author>
<name>Tero Kristo</name>
<email>t-kristo@ti.com</email>
</author>
<published>2015-02-12T09:32:14Z</published>
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<id>urn:sha1:7415b0b4c645fe9897352f144f056fd557526667</id>
<content type='text'>
This patch creates the l4_cfg and l4_wkup interconnects for OMAP4, and
moves some of the generic peripherals under it. System control module
support is added to the device tree also, and the existing SCM related
functionality is moved under it.

Signed-off-by: Tero Kristo &lt;t-kristo@ti.com&gt;
Reported-by: Tony Lindgren &lt;tony@atomide.com&gt;
</content>
</entry>
<entry>
<title>ARM: dts: am4372: add minimal l4 bus layout with control module support</title>
<updated>2015-03-31T18:26:56Z</updated>
<author>
<name>Tero Kristo</name>
<email>t-kristo@ti.com</email>
</author>
<published>2015-02-12T08:25:40Z</published>
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<id>urn:sha1:83a5d6c98af24bb4531dfc05e7c2d3ac2562c6d9</id>
<content type='text'>
This patch creates an l4_wkup interconnect for AM43xx, and moves some of
the generic peripherals under it. System control module nodes are moved
under this new interconnect also, and the SCM clock layout is changed
to use the renamed SCM nodea as the clock provider.

Signed-off-by: Tero Kristo &lt;t-kristo@ti.com&gt;
</content>
</entry>
<entry>
<title>ARM: dts: am33xx: add minimal l4 bus layout with control module support</title>
<updated>2015-03-31T18:26:56Z</updated>
<author>
<name>Tero Kristo</name>
<email>t-kristo@ti.com</email>
</author>
<published>2015-03-20T11:08:29Z</published>
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<id>urn:sha1:e3bc5358e0977b95652625f9329ba68f1ebb1a42</id>
<content type='text'>
This patch creates an l4_wkup interconnect for AM33xx, and moves some of
the generic peripherals under it. System control module nodes are moved
under this new interconnect also, and the SCM clock layout is changed
to use the renamed SCM node as the clock provider.

Signed-off-by: Tero Kristo &lt;t-kristo@ti.com&gt;
</content>
</entry>
<entry>
<title>ARM: dts: omap3: add minimal l4 bus layout with control module support</title>
<updated>2015-03-31T18:26:56Z</updated>
<author>
<name>Tero Kristo</name>
<email>t-kristo@ti.com</email>
</author>
<published>2015-02-24T14:22:45Z</published>
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<id>urn:sha1:b8845074cfbbd1d1b46720a1b563d7b4240dac21</id>
<content type='text'>
This patch creates an l4_core interconnect for OMAP3, and moves some
of the generic peripherals under it. System control module nodes are
moved under this new interconnect also, and the SCM clock layout
is changed to use the renamed SCM node as the clock provider.

Signed-off-by: Tero Kristo &lt;t-kristo@ti.com&gt;
Reported-by: Tony Lindgren &lt;tony@atomide.com&gt;
</content>
</entry>
<entry>
<title>ARM: dts: omap24xx: add minimal l4 bus layout with control module support</title>
<updated>2015-03-31T18:26:55Z</updated>
<author>
<name>Tero Kristo</name>
<email>t-kristo@ti.com</email>
</author>
<published>2015-02-12T08:38:16Z</published>
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<id>urn:sha1:72b10ac00eb1c154037e398371685d3f1d2d4793</id>
<content type='text'>
This patch creates an l4 / l4-wkup interconnects for omap2420 / omap2430
SoCs, and moves some of the generic peripherals under it. System control
module nodes are moved under this new interconnect also, and the SCM
clock layout is changed to use the new SCM node as the clock provider.

Signed-off-by: Tero Kristo &lt;t-kristo@ti.com&gt;
</content>
</entry>
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