kernel/Documentation/devicetree/bindings/arm/mediatek, branch linux-rolling-stable

dt-bindings: arm: mediatek: Support mt8183-audiosys variant

2025-09-26T19:50:44Z

Update the mediatek,audsys binding to support the mt8183-audiosys compatible, which uses a different audio controller (mediatek,mt8183-audio.yaml) compared to the legacy mt2701-audio controller. Reviewed-by: AngeloGioacchino Del Regno Reviewed-by: Rob Herring (Arm) Signed-off-by: Julien Massot Signed-off-by: Rob Herring (Arm)

dt-bindings: arm: mediatek: mmsys: Add OF graph support for board path

2024-10-22T09:10:26Z

Document OF graph on MMSYS/VDOSYS: this supports up to three DDP paths per HW instance (so potentially up to six displays for multi-vdo SoCs). The MMSYS or VDOSYS is always the first component in the DDP pipeline, so it only supports an output port with multiple endpoints - where each endpoint defines the starting point for one of the (currently three) possible hardware paths. Reviewed-by: Rob Herring (Arm) Reviewed-by: Alexandre Mergnat Tested-by: Alexandre Mergnat Reviewed-by: CK Hu Tested-by: Michael Walle # on kontron-sbc-i1200 Link: https://lore.kernel.org/r/20241017103809.156056-3-angelogioacchino.delregno@collabora.com Signed-off-by: AngeloGioacchino Del Regno

dt-bindings: clock: mediatek: Convert MediaTek clock syscons to schema

2024-08-12T20:51:18Z

Convert the various MediaTek syscon bindings which are a clock provider into DT schema format. As they are all the same other than compatible string, combine them into a single schema file. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20240807-dt-mediatek-clk-v1-3-e8d568abfd48@kernel.org Acked-by: Conor Dooley Signed-off-by: Stephen Boyd

dt-bindings: Move Mediatek clock controllers to "clock" directory

2024-08-12T20:51:15Z

The "arm" binding directory is for architecture specific and top-level board bindings. Move all the MediaTek bindings implementing clock providers from "arm/mediatek/" to "clock/" binding directories. Signed-off-by: Rob Herring (Arm) Link: https://lore.kernel.org/r/20240807-dt-mediatek-clk-v1-2-e8d568abfd48@kernel.org Acked-by: Conor Dooley Signed-off-by: Stephen Boyd

dt-bindings: clock: mediatek: convert SSUSBSYS to the json-schema clock

2024-02-22T04:56:37Z

This helps validating DTS files. Introduced changes: 1. Documented "reg" property 2. Dropped "syscon" as it was incorrectly used 3. Adjusted nodename, "compatible" and "reg" in example Signed-off-by: Rafał Miłecki Reviewed-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240214061233.24645-4-zajec5@gmail.com Signed-off-by: Stephen Boyd

dt-bindings: clock: mediatek: convert PCIESYS to the json-schema clock

2024-02-22T04:56:37Z

dt-bindings: clock: mediatek: convert hifsys to the json-schema clock

2024-02-22T04:56:37Z

This helps validating DTS files. Introduced changes: 1. Documented "reg" property 2. Documented "#reset-cells" property 3. Dropped "syscon" as it was incorrectly used 4. Adjusted "compatible" and "reg" in example Signed-off-by: Rafał Miłecki Reviewed-by: Krzysztof Kozlowski Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/20240214061233.24645-2-zajec5@gmail.com Signed-off-by: Stephen Boyd

Merge tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux

2024-01-12T21:42:35Z

Pull clk updates from Stephen Boyd: "Only a couple new SoCs have support added this time, primarily for Qualcomm SM8650 based on the diffstat. Otherwise this is a collection of non-critical fixes and cleanups to various clk drivers and their DT bindings. Nothing is changed in the core clk framework this time, although there's a patch to fix a basic clk type initialization function. In general, this pile looks to be on the smaller side. New Drivers: - Global, display, gpu, tcsr, and rpmh clocks on Qualcomm SM8650 - Mediatek MT7988 SoC clocks Updates: - Update Zynqmp driver for Versal NET platforms - Add clk driver for Versal clocking wizard IP - Support for stm32mp25 clks - Add glitch free PLL setting support to si5351 clk driver - Add DSI clocks on Amlogic g12/sm1 - Add CSI and ISP clocks on Amlogic g12/sm1 - Document bindings for i.MX93 ANATOP clock driver - Free clk_node in i.MX SCU driver for resource with different owner - Update the LVDS clocks to be compatible with i.MX SCU firmware 1.15 - Fix the name of the fvco in i.MX pll14xx by renaming it to fout - Add EtherNet TSN and PCIe clocks on the Renesas R-Car V4H SoC - Add interrupt controller and Ethernet clocks and resets on Renesas RZ/G3S - Check reset monitor registers on Renesas RZ/G2L-alike SoCs - Reuse reset functionality in the Renesas RZ/G2L clock driver - Global and RPMh clock support for the Qualcomm X1E80100 SoC - Support for the Stromer APCS PLL found in Qualcomm IPQ5018 - Add a new type of branch clock, with support for controlling separate memory control bits, to the Qualcomm clk driver - Use above new branch type in Qualcomm ECPRI clk driver for QDU1000 and QRU1000 - Add a number of missing clocks related to CSI2 on Qualcomm MSM8939 - Add support for the camera clock controller on Qualcomm SC8280XP - Correct PLL configuration in GPU and video clock controllers for Qualcomm SM8150 - Add runtime PM support and a few missing resets to Qualcomm SM8150 video clock controller - Fix configuration of various GCC GDSCs on Qualcomm SM8550 - Mark shared RCGs appropriately in the Qualcomm SM8550 GCC driver - Fix up GPU and display clock controllers PLL configuration settings on Qualcomm SM8550 - Cleanup variable init in Allwinner nkm module - Convert various DT bindings to YAML - A few kernel-doc fixes for Samsung SoC clock controllers" * tag 'clk-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/clk/linux: (93 commits) clk: mediatek: add drivers for MT7988 SoC clk: mediatek: add pcw_chg_bit control for PLLs of MT7988 dt-bindings: clock: mediatek: add clock controllers of MT7988 dt-bindings: reset: mediatek: add MT7988 ethwarp reset IDs dt-bindings: clock: mediatek: add MT7988 clock IDs clk: mediatek: mt8188-topckgen: Refactor parents for top_dp/edp muxes clk: mediatek: mt8195-topckgen: Refactor parents for top_dp/edp muxes clk: mediatek: clk-mux: Support custom parent indices for muxes dt-bindings: clock: sophgo: Add clock controller of CV1800 series SoC clk: starfive: jh7100: Add CLK_SET_RATE_PARENT to gmac_tx clk: starfive: Add flags argument to JH71X0__MUX macro clk: imx: pll14xx: change naming of fvco to fout clk: imx: clk-imx8qxp: fix LVDS bypass, pixel and phy clocks clk: imx: scu: Fix memory leak in __imx_clk_gpr_scu() clk: fixed-rate: fix clk_hw_register_fixed_rate_with_accuracy_parent_hw clk: qcom: dispcc-sm8650: Add test_ctl parameters to PLL config clk: qcom: gpucc-sm8650: Add test_ctl parameters to PLL config clk: qcom: dispcc-sm8550: Use the correct PLL configuration function clk: qcom: dispcc-sm8550: Update disp PLL settings clk: qcom: gpucc-sm8550: Update GPU PLL settings ...

dt-bindings: clock: mediatek: add clock controllers of MT7988

2024-01-03T23:55:17Z

Add various clock controllers found in the MT7988 SoC to existing bindings (if applicable) and add files for the new ethwarp, mcusys and xfi-pll clock controllers not previously present in any SoC. Signed-off-by: Daniel Golle Reviewed-by: AngeloGioacchino Del Regno Link: https://lore.kernel.org/r/07e76a544ce4392bcb88e34d5480e99bb7994618.1702849494.git.daniel@makrotopia.org Reviewed-by: Krzysztof Kozlowski Signed-off-by: Stephen Boyd

dt-bindings: arm: mediatek: move ethsys controller & convert to DT schema

2023-12-17T23:21:19Z

DT schema helps validating DTS files. Binding was moved to clock/ as this hardware is a clock provider. Example required a small fix for "reg" value (1 address cell + 1 size cell). Signed-off-by: Rafał Miłecki Reviewed-by: Rob Herring Link: https://lore.kernel.org/r/20231119212416.2682-1-zajec5@gmail.com Signed-off-by: Stephen Boyd