<feed xmlns='http://www.w3.org/2005/Atom'>
<title>kernel/Documentation/devicetree/bindings/arm/cpus.txt, branch linux-4.3.y</title>
<subtitle>Hosts the 0x221E linux distro kernel.</subtitle>
<id>https://universe.0xinfinity.dev/distro/kernel/atom?h=linux-4.3.y</id>
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<updated>2015-08-06T08:10:34Z</updated>
<entry>
<title>ARM: ux500: add an SMP enablement type and move cpu nodes</title>
<updated>2015-08-06T08:10:34Z</updated>
<author>
<name>Linus Walleij</name>
<email>linus.walleij@linaro.org</email>
</author>
<published>2015-08-03T07:26:41Z</published>
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<id>urn:sha1:bf64dd262eaaece2ff560e86fabf94c6725f3b5c</id>
<content type='text'>
The "cpus" node cannot be inside the "soc" node, while this
works for the CoreSight blocks, the early boot code will look
for "cpus" directly under the root node, so this is a hard
convention. So move the CPU nodes.

Augment the "reg" property to match what is actually in the
hardware: 0x300 and 0x301 respectively.

Then add an SMP enablement type to be used by the SMP init
code, "ste,dbx500-smp".

Signed-off-by: Linus Walleij &lt;linus.walleij@linaro.org&gt;
Signed-off-by: Olof Johansson &lt;olof@lixom.net&gt;
</content>
</entry>
<entry>
<title>ARM: sun8i: Add SMP support for the Allwinner A23</title>
<updated>2015-04-27T06:16:33Z</updated>
<author>
<name>Chen-Yu Tsai</name>
<email>wens@csie.org</email>
</author>
<published>2015-03-18T03:24:01Z</published>
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<id>urn:sha1:7917d14129a5a7241289f06d2c5299c5d03ed529</id>
<content type='text'>
The A23 is a dual Cortex-A7. Add the logic to use the IPs used to
control the CPU configuration and the CPU power so that we can
bring up secondary CPUs at boot.

Signed-off-by: Chen-Yu Tsai &lt;wens@csie.org&gt;
Signed-off-by: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>devicetree: bindings: add new SMP enable method for Marvell Armada 39x</title>
<updated>2015-03-04T14:35:34Z</updated>
<author>
<name>Thomas Petazzoni</name>
<email>thomas.petazzoni@free-electrons.com</email>
</author>
<published>2015-03-03T14:41:07Z</published>
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<id>urn:sha1:007fa9467f8f5607bb36b4a2bf31316a7e5b06ff</id>
<content type='text'>
This commit updates the ARM CPUs Device Tree binding to document a new
enable method of Marvell Armada 39x processors.

Signed-off-by: Thomas Petazzoni &lt;thomas.petazzoni@free-electrons.com&gt;
Signed-off-by: Gregory CLEMENT &lt;gregory.clement@free-electrons.com&gt;
</content>
</entry>
<entry>
<title>Documentation: DT bindings: add nvidia, tegra132-denver compatible string</title>
<updated>2015-02-04T02:43:49Z</updated>
<author>
<name>Paul Walmsley</name>
<email>paul@pwsan.com</email>
</author>
<published>2015-01-30T22:11:04Z</published>
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<id>urn:sha1:f634da375fc9675a978b36298579b5c2d87a6a8b</id>
<content type='text'>
Add a compatible string for the NVIDIA Denver CPU to the ARM CPU DT
binding documentation file.  The primary objective here is to keep
checkpatch.pl from warning when the compatible string is used in an
SoC DT file, per:

http://marc.info/?l=linux-tegra&amp;m=142201349727836&amp;w=2

This second version changes the string from "nvidia,denver" to
"nvidia,tegra132-denver" to more precisely describe the revision of
the Denver CPU complex that is present in the Tegra132 SoC.

Signed-off-by: Paul Walmsley &lt;paul@pwsan.com&gt;
Cc: Rob Herring &lt;robh+dt@kernel.org&gt;
Cc: Pawel Moll &lt;pawel.moll@arm.com&gt;
Cc: Mark Rutland &lt;mark.rutland@arm.com&gt;
Cc: Ian Campbell &lt;ijc+devicetree@hellion.org.uk&gt;
Cc: Kumar Gala &lt;galak@codeaurora.org&gt;
Cc: Heiko Stuebner &lt;heiko@sntech.de&gt;
Cc: Arnd Bergmann &lt;arnd@arndb.de&gt;
Cc: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Cc: Olof Johansson &lt;olof@lixom.net&gt;
Cc: Maxime Ripard &lt;maxime.ripard@free-electrons.com&gt;
Cc: Rohit Vaswani &lt;rvaswani@codeaurora.org&gt;
Cc: Paul Walmsley &lt;pwalmsley@nvidia.com&gt;
Cc: Marc Carino &lt;marc.ceeeee@gmail.com&gt;
Cc: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Cc: linux-kernel@vger.kernel.org
Cc: linux-arm-kernel@lists.infradead.org
Signed-off-by: Rob Herring &lt;robh@kernel.org&gt;
</content>
</entry>
<entry>
<title>ARM: rockchip: add option to access the pmu via a phandle in smp_operations</title>
<updated>2014-11-05T21:18:36Z</updated>
<author>
<name>Heiko Stuebner</name>
<email>heiko@sntech.de</email>
</author>
<published>2014-10-15T17:23:01Z</published>
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<id>urn:sha1:6de2d21adaf05b7a456077625b6e311feabd3718</id>
<content type='text'>
Makes it possible to define a rockchip,pmu phandle in the cpus node directly
referencing the pmu syscon instead of searching for specific compatible.

The old way of finding the pmu stays of course available.

Signed-off-by: Kever Yang &lt;kever.yang@rock-chips.com&gt;
Tested-by: Kevin Hilman &lt;khilman@linaro.org&gt;
Signed-off-by: Heiko Stuebner &lt;heiko@sntech.de&gt;
</content>
</entry>
<entry>
<title>Merge tag 'arm64-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc</title>
<updated>2014-10-08T21:40:02Z</updated>
<author>
<name>Linus Torvalds</name>
<email>torvalds@linux-foundation.org</email>
</author>
<published>2014-10-08T21:40:02Z</published>
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<id>urn:sha1:d5935b07da53f74726e2a65dd4281d0f2c70e5d4</id>
<content type='text'>
Pull ARM64 SoC changes from Arnd Bergmann:
 "Starting with 3.18, we are merging SoC-specific changes for arm64
  through the arm-soc tree, like we have been doing for arm32.

  This time, there is only one set of changes, adding support for the
  Cavium "Thunder" Soc family.  Since the changes are relatively small,
  this includes Kconfig, defconfig and DT changes.

  If all goes well, we will never require adding actual C source code
  for platform support in arm64, given that the architecture is more
  clearly defined and we have moved out a lot of the platform specifics
  into device drivers for arm32 already"

* tag 'arm64-for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/arm/arm-soc:
  arm64, defconfig: Enable Cavium Thunder SoC in defconfig
  arm64, thunder: Add Kconfig option for Cavium Thunder SoC Family
  arm64, thunder: Document devicetree bindings for Cavium Thunder SoC
  arm64, thunder: Add initial dts for Cavium Thunder SoC
</content>
</entry>
<entry>
<title>arm64, thunder: Document devicetree bindings for Cavium Thunder SoC</title>
<updated>2014-10-02T15:38:43Z</updated>
<author>
<name>Radha Mohan Chintakuntla</name>
<email>rchintakuntla@cavium.com</email>
</author>
<published>2014-04-08T13:23:14Z</published>
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<id>urn:sha1:4c3087008dd19dcfced1bbbc2414ac5a8a61bcef</id>
<content type='text'>
This patch adds documentation for the devicetree bindings used by the
DT files of Cavium Thunder SoC platforms.

Signed-off-by: Radha Mohan Chintakuntla &lt;rchintakuntla@cavium.com&gt;
Signed-off-by: Robert Richter &lt;rrichter@cavium.com&gt;
Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>Documentation: arm: define DT idle states bindings</title>
<updated>2014-09-12T09:48:55Z</updated>
<author>
<name>Lorenzo Pieralisi</name>
<email>lorenzo.pieralisi@arm.com</email>
</author>
<published>2013-11-27T16:22:55Z</published>
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<id>urn:sha1:3f8161b260cb9232bb926a5d6c1cc2672fea07c7</id>
<content type='text'>
ARM based platforms implement a variety of power management schemes that
allow processors to enter idle states at run-time.
The parameters defining these idle states vary on a per-platform basis forcing
the OS to hardcode the state parameters in platform specific static tables
whose size grows as the number of platforms supported in the kernel increases
and hampers device drivers standardization.

Therefore, this patch aims at standardizing idle state device tree bindings
for ARM platforms. Bindings define idle state parameters inclusive of entry
methods and state latencies, to allow operating systems to retrieve the
configuration entries from the device tree and initialize the related power
management drivers, paving the way for common code in the kernel to deal with
idle states and removing the need for static data in current and previous
kernel versions.

ARM64 platforms require the DT to define an entry-method property
for idle states.

On system implementing PSCI as an enable-method to enter low-power
states the PSCI CPU suspend method requires the power_state parameter to
be passed to the PSCI CPU suspend function.

This parameter is specific to a power state and platform specific,
therefore must be provided by firmware to the OS in order to enable
proper call sequence.

Thus, this patch also adds a property in the PSCI bindings that
describes how the PSCI CPU suspend power_state parameter should be
defined in DT in all device nodes that rely on PSCI CPU suspend method usage.

Acked-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
Acked-by: Daniel Lezcano &lt;daniel.lezcano@linaro.org&gt;
Acked-by: Nicolas Pitre &lt;nico@linaro.org&gt;
Reviewed-by: Rob Herring &lt;robh@kernel.org&gt;
Reviewed-by: Sebastian Capella &lt;sebcape@gmail.com&gt;
Signed-off-by: Lorenzo Pieralisi &lt;lorenzo.pieralisi@arm.com&gt;
Signed-off-by: Catalin Marinas &lt;catalin.marinas@arm.com&gt;
</content>
</entry>
<entry>
<title>Merge tag 'for-3.17/bcm-dt' of git://github.com/broadcom/mach-bcm into next/dt</title>
<updated>2014-07-28T15:05:59Z</updated>
<author>
<name>Arnd Bergmann</name>
<email>arnd@arndb.de</email>
</author>
<published>2014-07-28T15:05:17Z</published>
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<id>urn:sha1:8cfb4e3d302680baa9d425a8175bb86d3d0443e3</id>
<content type='text'>
Merge "ARM: mach-bcm: dt updatees for 3.17" from Matt Porter:

- BCM Mobile SMP support
- BRCM STB platform support

* tag 'for-3.17/bcm-dt' of git://github.com/broadcom/mach-bcm:
  ARM: brcmstb: dts: add a reference DTS for Broadcom 7445
  ARM: brcmstb: gic: add compatible string for Broadcom Brahma15
  ARM: brcmstb: add misc. DT bindings for brcmstb
  ARM: brcmstb: add CPU binding for Broadcom Brahma15
  ARM: dts: enable SMP support for bcm21664
  ARM: dts: enable SMP support for bcm28155
  devicetree: bindings: document Broadcom CPU enable method

Signed-off-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
</content>
</entry>
<entry>
<title>ARM: brcmstb: add CPU binding for Broadcom Brahma15</title>
<updated>2014-07-28T14:00:57Z</updated>
<author>
<name>Marc Carino</name>
<email>marc.ceeeee@gmail.com</email>
</author>
<published>2013-09-06T20:40:19Z</published>
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<id>urn:sha1:0a540d4ba6af544121ca04cbb8ee14212a6e645a</id>
<content type='text'>
Add the Broadcom Brahma B15 CPU to the DT CPU binding list.

Signed-off-by: Marc Carino &lt;marc.ceeeee@gmail.com&gt;
Acked-by: Arnd Bergmann &lt;arnd@arndb.de&gt;
Signed-off-by: Brian Norris &lt;computersforpeace@gmail.com&gt;
Signed-off-by: Matt Porter &lt;mporter@linaro.org&gt;
</content>
</entry>
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