#include "ExecutorCases.h" #include "Instruction.h" #include "Bus.h" #include #include CPUContext::CPUContext(Instruction& i, uint32_t& ip, uint32_t& flags, uint32_t* reg, std::shared_ptr& bus, bool& isHalted) : m_Instruction(i), m_InstructionPointer(ip), m_Flags(flags), m_Registers(reg), m_Bus(bus), m_IsHalted(isHalted) { } CPUContext::~CPUContext() = default; // NO SIB SUPPORT YET namespace executor_cases { void Nop(CPUContext& cc){ std::cout << "No op" << std::endl; } void Hlt(CPUContext& cc){ std::cout << "Program halted!" << std::endl; exit(0); } void Mov_r32_imm32(CPUContext& cc){ cc.m_Registers[cc.m_Instruction.m_Operand1] = cc.m_Instruction.m_Operand2; } void Add_rm32_r32(CPUContext& cc){ x86::ModRM modrm = cc.m_Instruction.optional.m_ModRM; switch(modrm.m_State) { case x86::ModRMState::R: { cc.m_Registers[modrm.m_Rm] += cc.m_Registers[modrm.m_Reg]; break; } case x86::ModRMState::LR: { uint32_t dstPrevValue = cc.m_Bus->AccessX(cc.m_Registers[modrm.m_Rm]); uint32_t currRegValue = cc.m_Registers[modrm.m_Reg]; uint32_t result = dstPrevValue + currRegValue; cc.m_Bus->WriteX(cc.m_Registers[modrm.m_Rm], result); break; } case x86::ModRMState::LR_DISP8: { uint32_t dstAddress = cc.m_Registers[modrm.m_Rm] + cc.m_Instruction.m_Operand2; uint32_t dstPrevValue = cc.m_Bus->AccessX(dstAddress); uint32_t currRegValue = cc.m_Registers[modrm.m_Reg]; uint32_t result = dstPrevValue + currRegValue; cc.m_Bus->WriteX(dstAddress, result); break; } default: { throw std::runtime_error("Invalid ModRM State encountered during Add_rm32_r32"); } } } } constexpr std::array GenerateExecutorTable(){ std::array table{}; table[Opcode::NOP] = executor_cases::Nop; table[Opcode::HLT] = executor_cases::Hlt; table[Opcode::MOV_R_IMM32] = executor_cases::Mov_r32_imm32; table[Opcode::ADD_RM32_R32] = executor_cases::Add_rm32_r32; return table; } static constexpr std::array s_ExecutorTable = GenerateExecutorTable(); const std::array& GetExecutorTable() { return s_ExecutorTable; }