Feature: Add mov_rm32_r32 instruction & more expressive execution with CPU trace

src/CPU.cpp

@@ -3,6 +3,7 @@
 #include <stdexcept>
 #include <iostream>
 #include <iomanip>
+#include <bitset>
 #include <stdlib.h>
 #include <array>
 #include <cassert>
@@ -10,10 +11,15 @@
 CPU::CPU(std::shared_ptr<Bus> bus) : m_Bus(bus), m_IsHalted(false), m_Context({m_Instruction, m_InstructionPointer, m_Flags, m_Registers, m_Bus, m_IsHalted}) {
   m_InstructionPointer = 0x00008000;
 
-  for(int i = 0; i < 16; i++)
+  for(int i = 0; i < 8; i++)
   {
     m_Registers[i] = 0;
   }
+
+  for(int i = 0; i < 8; i++)
+  {
+    m_SegmentRegisters[i] = 0;
+  }
 }
 
 void CPU::Step() {
@@ -21,6 +27,23 @@ void CPU::Step() {
   Execute();
 }
 
+void CPU::Dump() {
+  std::cout << "--TRACE-- ";
+  std::cout << std::endl;
+  
+  for(uint8_t i = 0; i < 8; i++)
+  {
+    std::cout << x86::Register2Str((x86::Register)i) << ": " << m_Registers[i] << " | ";
+  }
+
+  std::cout << std::endl;
+
+  std::bitset<32> flags(m_Flags);
+  std::cout << "IP: " << std::hex << m_InstructionPointer << " | FLAGS: " << flags;
+  
+  std::cout << std::endl;
+}
+
 void CPU::FetchDecode() {
   uint8_t opcode_raw = m_Bus->AccessX<uint8_t>(m_InstructionPointer);
   Opcode opcode = static_cast<Opcode>(opcode_raw);
@@ -43,18 +66,24 @@ void CPU::FetchDecode() {
     m_Instruction.m_Length = 2;
     FetchModRMFields();
     break;
+  case Opcode::MOV_RM32_R32:
+    m_Instruction.m_Opcode = opcode;
+    m_Instruction.optional.m_ModRM = x86::process_modrm(m_Bus->AccessX<uint8_t>(m_InstructionPointer + 1));
+    m_Instruction.m_Length = 2;
+    FetchModRMFields();
+    break;
   }
 
   m_InstructionPointer += m_Instruction.m_Length;
 }
 
 void CPU::Execute() {
-  std::cout << "Executing... \n";
   uint8_t opcode_value = static_cast<uint8_t>(m_Instruction.m_Opcode);
   auto& exec_table = GetExecutorTable();
   if(exec_table[opcode_value])
   {
     exec_table[opcode_value](m_Context);
+    Dump();
     return;
   }
   throw std::runtime_error("Opcode not found!");